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| 1 datasheet precision digital power monitor with margining isl28023 the isl28023 is a bidirectional high-side and low-side digital current sense and voltage monitor with a serial interface. the device monitors power supply current, voltage and provides the digital results along with calculated power. the isl28023 provides tight accuracy of 0.05% for both voltage and current monitoring. the auxiliary input provides an additional power monitor function. the v cc power can either be externally supplied or internally regulated, which allows the isl28023 to handle a common-mode input voltage range from 0v to 60v. the wide range permits the device to handle telecom, automotive and industrial applications with minimal external circuitry. an 8-bit voltage dac enables a dc/dc converter output voltage margining. fault indication includes a bus voltage window and overcurrent fast fault logic indication. a temperature sensing option includes both internal temperature sensor and a bias/m onitor circuit for external diode sensing. the isl28023 serial interface is pmbus compatible and operates down to 1.2v voltage. it draws an average current of just 800a and is available in the space saving 24 ld qfn 4mmx4mm package. the part operates across the full industrial temper ature range from -40c to +125c. related literature an1955 , ?design ideas for intersil digital power monitors? features ? bus voltage sense range . . . . . . . . . . . . . . . . . . . . . . 0v to 60v ? voltage gain error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05% ? current gain error. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.05% ? internal temperature sensor accuracy . . . . . . . . . . . . +1.0c ? high or low (rtn) side sensing ? bidirectional current sensing ? auxiliary low voltage channel ? ? adc, 16-bit native resolution ? programmable averaging modes ? internal 3.3v regulator ? internal temperature sense ? overvoltage/undervoltage and cu rrent fault monitoring with 500ns detection delay ?8-bit voltage output dac ?i 2 c/smbus/pmbus interface th at handles 1.2v supply ? 55 i 2 c slave addresses applications ? data processing servers ? dc power distribution ? telecom equipment ? portable communication equipment ? dc/dc, ac/dc converters ?many i 2 c dac and adc with alert applications figure 1. application diagram load vout = 0.6 + (0.6 C dac out) * r2/r1 i 2 c smbus a1 scl sda vinp gnd adc 16-bit sw mux pmbus reg map a0 isl28023 vcc vinm vbus fb isl85415 en pg gnd vcc,fs,ss vin a2 8-bit dac dac out lo phase sync,comp 1f to smbalert1 0.1f boot v in = 4.5v ? 36v r 2 r 1 r 3 vmcu gnd gpio/int sda gpio scl r_pullup r_pullup mcu smbalert2 i2cvcc 3.3v vreg vreg_in vreg_out v in rsh auxv auxp auxm ext_temp place diode near rsh temp sense v in smbalert1 june 17, 2015 fn8389.4 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2014, 2015. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl28023 2 fn8389.4 june 17, 2015 submit document feedback table of contents block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 typical performance curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 communication protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 packet error correction (pec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 ic device details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 global ic controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 primary and auxiliary channel controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 measurement registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 threshold detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 smb alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 external clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 voltage margin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 smbus/i 2 c serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 smbus, pmbus support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 group command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 clock speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 signal integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 fast transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 external clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 overranging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 shunt resistor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 lossless current sensing (dcr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 a trace as a sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 about intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 isl28023 3 fn8389.4 june 17, 2015 submit document feedback block diagram figure 2. block diagram fir and digital logic i 2 c sm bus pm bus a0 16 a1 smbclk smbdat osc smbalert1 vinp vinm vbus gnd adc 16- bit reg map ref temp sense ov_temp_set oc_set vbus_s 3.3v internal power auxp auxm clock uv_set reg vin_m vin_p dac_out dac (8-bit) sw mux oc dac ov/ temp dac uv dac i2cvcc smbalert2 ls ls cm = 0 to 60v cm = 0 to vcc a2 auxv vreg_in vreg_out vcc digital filter 0, 2, 4, 8 s div vbus_s temp_v vbus_s temp_v only for pri chl ext_clk { primary ch aux ch { ordering information part number ( notes 1 , 2 , 3 ) part marking v bus option (v) package (rohs compliant pkg. dwg. # isl28023fr12z 280 23r12z 12 24 ld qfn l24.4x4d isl28023fr60z 280 23r60z 60 24 ld qfn l24.4x4d isl28023eval1z evaluation board ISL28023EVKIT1Z evaluation kit notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb-free products are msl classified at pb-fr ee peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jed ec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl28023 . for more information on msl please see techbrief tb363 . isl28023 4 fn8389.4 june 17, 2015 submit document feedback pin configuration isl28023 (24 ld qfn) top view vbus vreg_in vinp vinm nc vreg_out smbclk smbdat nc smbalert1 smbalert2 ext_clk nc gnd auxp auxm auxv dac_out vcc i2cvcc a2 a1 a0 gnd 1 2 3 4 5 6 18 17 16 15 14 13 24 23 22 21 20 19 7 8 9 10 11 12 gnd pin descriptions pin number pin name type/dir pin definition 1, 9, 20 nc n/a no connect 2gnd powerground 3 auxp analog input auxiliary port differential input (plus) 4 auxm analog input auxiliary port differential input (minus) 5 auxv analog input auxiliary port single ended input 6 dac_out analog output dac voltage output 7 smbclk digital input smbus/i 2 c clock input 8 smbdat digital input/output smbus/i 2 c data 10 smbalert1 digital output smbus alert1, open-drain output 11 smbalert2 digital output cpu interrupt signal: it is used as cpu interrupt signal 12 ext_clk digital input external adc clock input 13 gnd power ground 14 a0 digital input smbus/i 2 c address input 15 a1 digital input smbus/i 2 c address input 16 a2 digital input smbus/i 2 c address input 17 i2cvcc power i 2 c level shifter power supply. this pin should be connected to vcc pin if level shifter is not used. 18 vcc power chip power supply 19 vreg_out power voltage regulator output, proper deco upling capacitor should be connected to this pin 21 vinm analog input current sense minus input 22 vinp analog input current sense plus input 23 vreg_in power voltage regulator input. this pin should be connected to ground in case voltage regulator is not used. 24 vbus power vbus voltage sense isl28023 5 fn8389.4 june 17, 2015 submit document feedback table 1. dpm portfolio comparison - isl28022 vs isl28023 vs isl28025 description basic digital power monitor full feature digital power monitor digital power monitor in tiny package part number isl28022 isl28023 isl28025 package msop10, qfn16 qfn24 wlcsp-16 temperature range -40c to +125c -40c to +125c -40c to +125c 0v to 60v input range 0v to 60v opt 1: 0v to 60v opt 2: 0v to 16v opt 1: 0v to 60v opt 2: 0v to 16v adc 16-bit 16-bit 16-bit 25c gain error 0.30% 0.25% 0.25% current measure lsb step 10v 2.5v 2.5v 25c offset 75v 30v 30v primary differential shunt input x x x channel independent bus voltage x x x lv aux differential shunt input x channel independent bus voltage x x vbus lsb step low voltage bus 0.25mv 0.25mv high voltage bus 4mv 1mv/0.25mv 1mv/0.25mv external temperature sensor input x hv internal regulator (3.3v out )xx fast oc/ov/uv alert outputs 2 outputs 2 outputs margin dac x internal temperature sensor x x user select conversion mode/sample rate x x x peak min/max current registers x x slave address locations 16 addresses 55 addresses 55 addresses i 2 c level translators xx pmbus xx i 2 c/smbus x x x high speed (3.4mhz) i 2 c mode x x x external clock input x x x power shutdown mode x x x isl28023 6 fn8389.4 june 17, 2015 submit document feedback absolute maximum rating s thermal information vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0v i2cvcc voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0v vbus (isl28023fr60), vreg_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63v vbus (isl28023fr12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.684v common mode input voltage (vinp, vinm). . . . . . . . . . . . . . . . . . . . . . . 63v differential input voltage (vinp, vinm) . . . . . . . . . . . . . . . . . . . . . . . . . 63v auxv. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vcc-gnd common mode input voltage (auxp, auxm) . . . . . . . . . . . . . . . . . vcc-gnd differential input voltage (auxp, auxm) . . . . . . . . . . . . . . . . . . . . .vcc-gnd input voltage (digital pins) . . . . . . . . . . . . . . . . . gnd-0.3 to i2cvcc + 0.3v output voltage (digital pins) . . . . . . . . . . . . . . . . gnd-0.3 to i2cvcc + 0.3v output current (vreg_out, dac_out) . . . . . . . . . . . . . . . . . . . . . . . . 10ma open-drain output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma open-drain voltage (smbalert1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24v esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . . . 6kv machine model (tested per jesd22-a115). . . . . . . . . . . . . . . . . . . . 300v charged device model (tested per jesd22-c101). . . . . . . . . . . . . . . 2kv latch-up (tested per jesd-78b) . . . . . . . . . . . . . . . . . 100ma (at +125c) thermal resistance (typical) ? ja (c/w) ? jc (c/w) 24 ld qfn ( notes 4 , 5 ) . . . . . . . . . . . . . . . . 38 2.5 maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c maximum junction temperature (t jmax ) . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions ambient temperature range (t a ) . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications t a = +25c, i 2 cvcc = v cc = 3.3v, v inp = v bus = 12v, v sense = v inp -v inm = 80mv, auxp-auxm = 80mv, auxv = 3v, conversion time: aux = primary = 2.05ms, internal avg aux = prim ary = 128, unless otherwise specified. all voltages with respec t to gnd pin. parameter description test conditions min ( note 6 )typ max ( note 6 )unit primary channel v shunt v shunt measurement range (v inp - v inm )081.91mv step_shunt 1lsb step shunt voltage 2.5 v vshunt_vos v shunt offset voltage 2.5 50 v vshunt_tc v shunt offset voltage vs temperature t = -40c to +125c 0.04 0.3 v/c vshunt_cmrr v shunt vos vs common mode isl28023fr60z v bus = 0v to 60v 0.16 1.6 v/v isl28023fr12z v bus = 0v to 16.384v 0.16 1.6 v/v vshunt_psrr v shunt vos vs power supply v cc = 10% of v cc nominal 0.45 v/v ivin v in input leakage current v in = v shunt input path selected, oc detector disabled 15 20 a v in = v shunt input path selected, oc detector enabled 30 40 a v in = v shunt input path disabled, oc detector disabled 0.05 0.1 a v bus usable bus voltage measurement range isl28023fr60z 0 60 v isl28023fr12z 0 16.384 v step_vbus 1lsb step bus voltage isl28023fr60z 1 mv isl28023fr12z 0.25 mv isl28023 7 fn8389.4 june 17, 2015 submit document feedback vbus_vos v bus offset voltage isl28023fr60z -20 1 20 mv isl28023fr12z -5 1.5 5 mv vbus_tc v bus offset voltage vs temperature isl28023fr60z; t = -40c to +125c 4 100 v/c isl28023fr12z; t = -40c to +125c 4 100 v/c vbus_vco v bus voltage coefficient 50 ppm/v vbus_psrr v bus vos vs power supply isl28023fr60z; v cc = 10% of v cc nominal 500 v/v isl28023fr12z v cc = 10% of v cc nominal 125 v/v zin_vbus input impedance v bus isl28023fr60z 600 k isl28023fr12z 150 k aux channel vshunt_aux v shunt aux measurement range (auxp - auxm) 081.91mv step_shunt_aux 1lsb step shunt aux voltage 2.5 v vshunt_aux_vos v shunt aux offset voltage 2.5 50 v vshunt_aux_tc v shunt aux offset voltage vs temperature t = -40c to +125c 0.01 0.1 v/c vshunt_aux_cmrr v shunt aux vos vs common mode v bus = 0v to vcc 0.1 4 v/v vshunt_aux_psrr v shunt aux vos vs power supply v cc = 10% of v cc nominal 0.45 v/v zin_aux_in aux input impedance aux = auxvshunt input path selected 1 m aux = auxvshunt input path disabled 10 m vauxv usable avxv voltage measurement range 0 vcc v step_auxv 1lsb step auxv voltage 100 v vauxv_vos vauxv offset voltage 0.3 4 mv vauxv_tc vauxv offset voltage vs temperature t = -40c to +125c 0.2 22 v/c vauxv_psrr vauxv vos vs power supply v cc = 10% of v cc nominal 1 mv/v zin_auxv auxv input impedance input path selected 200 k input path disabled 10 m adc parameters adc resolution 16 bits primary shunt voltage gain error 0.05 0.25 % t = -40c to +125c 60 ppm/c primary bus voltage gain error 0.05 0.2 % t = -40c to +125c 10 70 ppm/c aux shunt voltage gain error 0.02 0.25 % t = -40c to +125c 65 ppm/c aux bus voltage gain error 0.02 0.2 % t = -40c to +125c 65 ppm/c differential non-linearity 1 lsb electrical specifications t a = +25c, i 2 cvcc = v cc = 3.3v, v inp = v bus = 12v, v sense = v inp -v inm = 80mv, auxp-auxm = 80mv, auxv = 3v, conversion time: aux = primary = 2.05ms, internal avg aux = prim ary = 128, unless otherwise specified. all voltages with respec t to gnd pin. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )unit isl28023 8 fn8389.4 june 17, 2015 submit document feedback adc timing t s power-up adc conversion time resolution adc[2:0] = 0h 64 70.4 s adc[2:0] = 1h 128 140.8 s adc[2:0] = 2h 256 281.6 s adc[2:0] = 3h 512 563.2 s adc[2:0] = 4, 5h 1.024 1.126 ms adc[2:0] = 6, 7h 2.048 2.253 ms threshold detectors overvoltage (ov) v bus threshold voltage range vbus_thres_rng[2:0] = all 25 125 % of fs overvoltage (ov) v bus threshold dac step size vbus_thres_rng[2:0] = all 1.56 % of fs undervoltage (uv) v bus threshold voltage range vbus_thres_rng[2:0] = all 0 100 % of fs undervoltage (uv) v bus threshold dac step size vbus_thres_rng[2:0] = all 1.56 % of fs v bus threshold detector full-scale settings isl28025fi60z vbus_thres_rng[2:0] = 0; ot_sel = 0 48 v vbus_thres_rng[2:0] = 1; ot_sel = 0 24 v vbus_thres_rng[2:0] = 2; ot_sel = 0 12 v vbus_thres_rng[2:0] = 3; ot_sel = 0 5 v vbus_thres_rng[2:0] = 4; ot_sel = 0 3.3 v vbus_thres_rng[2:0] = 5; ot_sel = 0 2.5 v v bus threshold detector full-scale settings isl28025fi12z vbus_thres_rng[2:0] = 0; ot_sel = 0 12 v vbus_thres_rng[2:0] = 1; ot_sel = 0 6 v vbus_thres_rng[2:0] = 2; ot_sel = 0 3 v vbus_thres_rng[2:0] = 3; ot_sel = 0 2.5 v vbus_thres_rng[2:0] = 4; ot_sel = 0 0.825 v vbus_thres_rng[2:0] = 5; ot_sel = 0 0.625 v over-temperature threshold detector range ot_sel = 1 -40 135 c over-temperature threshold detector resolution error 5 c overcurrent (oc) v shunt threshold voltage range ocrng = all 25 125 % of fs overcurrent (oc) v shunt threshold dac step size ocrng = all 1.56 % of fs v shunt threshold detector full-scale settings ocrng = 0 80 mv ocrng = 1 40 mv margining dac, analog output resolution 8bits dnl 1 lsb electrical specifications t a = +25c, i 2 cvcc = v cc = 3.3v, v inp = v bus = 12v, v sense = v inp -v inm = 80mv, auxp-auxm = 80mv, auxv = 3v, conversion time: aux = primary = 2.05ms, internal avg aux = prim ary = 128, unless otherwise specified. all voltages with respec t to gnd pin. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )unit isl28023 9 fn8389.4 june 17, 2015 submit document feedback inl mdac[7:0] = 0 to 256 3 lsb gain error dac_ms[2:0] = 0 2.5 % offset error dac_ms[2:0] = 0 2 mv output voltage 0.055 2*vms v vms dac mid-scale dac_ms[2:0] = 0 0.4 v dac_ms[2:0] = 1 0.5 v dac_ms[2:0] = 2 0.6 v dac_ms[2:0] = 3 0.7 v dac_ms[2:0] = 4 0.8 v dac_ms[2:0] = 5 0.9 v dac_ms[2:0] = 6 1.0 v dac_ms[2:0] = 7 1.2 v slew rate 1v/s output current 1ma short circuit current dac_out = v cc 17 ma dac_out = gnd 4.2 ma start-up time 100 s voltage regulator specification input voltage at reg_in 4.5 60 v output regulation voltage 3.18 3.3 3.35 v line regulation v in = 4.5v to 60v 53 150 v/v load regulation i load = 3.3ma to 6ma 0.2 1.4 mv/ma capacitance drive 0.01 10 f output short circuit t = -40c to +125c 10 ma max load current t = -40c to +125c 6 ma start-up time 1ms temperature sensor temperature sensor measurement range -40 125 c temperature accuracy t = +25c +1 c temperature resolution 0.5 c measurement time 0.5 ms smbus/i 2 c interface specifications v il smbdat and smbclk input buffer low voltage -0.3 0.3 x i2cvcc v v ih smbdat and smbclk input buffer high voltage 0.7 x i2cvcc i2cvcc + 0.3 v hysteresis smbdat and smbclk input buffer hysteresis 0.05 x i2cvcc v v ol smbdat output buffer low voltage, sinking 3ma i 2 cvcc = 5v, i ol = 3ma 0 0.02 0.4 v electrical specifications t a = +25c, i 2 cvcc = v cc = 3.3v, v inp = v bus = 12v, v sense = v inp -v inm = 80mv, auxp-auxm = 80mv, auxv = 3v, conversion time: aux = primary = 2.05ms, internal avg aux = prim ary = 128, unless otherwise specified. all voltages with respec t to gnd pin. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )unit isl28023 10 fn8389.4 june 17, 2015 submit document feedback c pin smbdat and smbclk pin capacitance t a = +25c, f = 1mhz, i 2 cvcc = 5v, v in =0v, v out = 0v 10 pf f smbclk smbclk frequency 400 khz t in pulse width suppression time at smbdat and smbclk inputs any pulse narrower than the max spec is suppressed 50 ns t aa smbclk falling edge to smbdat output data valid smbclk falling edge crossing 30% of i 2 cvcc, until smbdat exits the 30% to 70% of i 2 cvcc window 900 ns t buf time the bus must be free before the start of a new transmission smbdat crossing 70% of i 2 cvcc during a stop condition, to smbdat crossing 70% of i 2 cvcc during the following start condition 1300 ns t low clock low time measured at the 30% of i 2 cvcc crossing 1300 ns t high clock high time measured at the 70% of i 2 cvcc crossing 600 ns t su:sta start condition setup time smbclk rising edge to smbdat falling edge. both crossing 70% of i 2 cvcc 600 ns t hd:sta start condition hold time from smbdat falling edge crossing 30% of i 2 cvcc to smbclk falling edge crossing 70% of i 2 cvcc 600 ns t su:dat input data setup time from smbdat exiting the 30% to 70% of v cc window, to smbclk rising edge crossing 30% of i 2 cvcc 100 ns t hd:dat input data hold time from smbclk falling edge crossing 30% of i 2 cvcc to smbdat entering the 30% to 70% of i 2 cvcc window 20 900 ns t su:sto stop condition setup time from smbclk rising edge crossing 70% of i 2 cvcc, to smbdat rising edge crossing 30% of i 2 cvcc 600 ns t hd:sto stop condition hold time from sm bdat rising edge to smbclk falling edge. both crossing 70% of i 2 cvcc 600 ns t dh output data hold time from smbclk falling edge crossing 30% of i 2 cvcc, until smbdat enters the 30% to 70% of i 2 cvcc window 0ns t r smbdat and smbclk rise time from 30% to 70% of i 2 cvcc 20 + 0.1 x cb 300 ns t f smbdat and smbclk fall time from 70% to 30% of i 2 cvcc 20 + 0.1 x cb 300 ns cb capacitive loading of smbdat or smbclk total on-chip and off-chip 10 400 pf r pu smbdat and smbclk bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ~2.5k for cb = 40pf, max is about 15k ~20k 1k power supply vvcc power supply voltage at v cc 3.0 3.3 5.5 v vi2cvcc power supply voltage at i 2 cvcc f = dc to 400khz 1.2 3.3 5.5 v only adc in conversion mode all other blocks are disabled 690 830 a electrical specifications t a = +25c, i 2 cvcc = v cc = 3.3v, v inp = v bus = 12v, v sense = v inp -v inm = 80mv, auxp-auxm = 80mv, auxv = 3v, conversion time: aux = primary = 2.05ms, internal avg aux = prim ary = 128, unless otherwise specified. all voltages with respec t to gnd pin. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )unit isl28023 11 fn8389.4 june 17, 2015 submit document feedback only adc in idle mode all other blocks are disabled 640 705 a only threshold detectors all three detectors are active 760 945 a only margin dac all other blocks are disabled 240 286 a fully enabled chip current all functional blocks enabled 1240 1545 a fully disabled chip current all functional blocks disabled 5 15 a ivreg_in voltage regulator vreg_in = 4.5v to 60v; rload = open 26 35 a ii2cvcc i 2 c supply current smbclk = 100khz; i 2 cvcc = 3.3v 15 a ii2cvcc_pd i 2 c idle supply current input signals are static 100 na note: 6. parameters with min and/or max limits ar e 100% tested at +25c, unless otherwise spec ified. compliance to datasheet limits is assured by one or more of the following methods: production test, characterization and design. electrical specifications t a = +25c, i 2 cvcc = v cc = 3.3v, v inp = v bus = 12v, v sense = v inp -v inm = 80mv, auxp-auxm = 80mv, auxv = 3v, conversion time: aux = primary = 2.05ms, internal avg aux = prim ary = 128, unless otherwise specified. all voltages with respec t to gnd pin. (continued) parameter description test conditions min ( note 6 )typ max ( note 6 )unit isl28023 12 fn8389.4 june 17, 2015 submit document feedback typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. figure 3. primary v shunt v os figure 4. primary v shunt v os vs vcc figure 5. primary v shunt v os tc (-40c to +125c) figure 6. primary v shunt vos vs temperature figure 7. primary v shunt cmrr, cmv = (0v to 60v) figure 8. primary v shunt cmrr vs temperature (cmv = 0v to 60v) 0 1 2 3 4 5 6 7 8 9 -50.0 -37.5 -25.0 -12.5 0 12.5 25.0 37.5 50.0 v os (v) hits -50 -40 -30 -20 -10 0 10 20 30 40 50 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) v os (v) t = -40c t = +25c t = +125c 0 1 2 3 4 5 6 7 -0.300 -0.225 -0.150 -0.075 0 0.075 0.150 0.225 0.300 v os tc (v/c) hits -40 -20 0 20 40 60 80 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) v os (v) v cc = 5v v cc = 3v v cc = 3.3v 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -500 -375 -250 -125 0 125 250 375 500 primary cmrr (nv/v) hits -500 -400 -300 -200 -100 0 100 200 300 400 500 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) cmrr (nv/v) isl28023 13 fn8389.4 june 17, 2015 submit document feedback figure 9. primary v shunt cmrr vs cmv figure 10. primary v shunt ac cmrr vs frequency figure 11. primary v shunt common mode range figure 12. smbalert current drives figure 13. primary v shunt adc gain error figure 14. primary v shunt adc gain error tc typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -20 -15 -10 -5 0 5 10 15 20 0 8 16 24 32 40 48 56 64 cmv (v) v os (v) 90 95 100 105 110 115 120 125 130 10 100 1k 10k 100k frequency (hz) cmrr (db) time = 0.128ms time = 2.048ms time = 1.024ms time = 0.512ms time = 0.256ms time = 0.64ms 35 45 55 65 75 85 95 -80 -70 -60 -50 -40 -30 -20 -10 0 cmv (mv) v meas (mv p-p ) v input = 80mv p-p sine wave to cmv = 60v frequency = 100hz adc timing = 64s 0 20 40 60 80 100 120 140 160 180 0.01 0.1 1 10 current load (ma) abs (change in voltage) (mv) smbalert1 sink smbalert2 source smbalert2 sink 0 1 2 3 4 5 6 7 8 -0.20 -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 gain error (%) hits 0 1 2 3 4 5 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 v shunt gain error tc (ppm/c) hits isl28023 14 fn8389.4 june 17, 2015 submit document feedback figure 15. primary v shunt measurement error vs in put figure 16. primary v shunt measurement error vs temperature figure 17. primary v shunt bandwidth vs adc timing figure 18. primary v shunt and v bus vs frequency figure 19. primary v bus v os figure 20. primary v bus v os vs v cc typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 v input (v) measurement error (%) v cc = 5v v cc = 3v + 3.3v -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) measurement error (%) v cc = 5v v cc = 3v v cc = 3.3v -15 -13 -11 -9 -7 -5 -3 -1 1 10 100 1k 10k 100k frequency (hz) gain (db) time = 2.048ms time = 1.024ms time = 0.512ms time = 0.256ms time = 0.128ms 50mv p-p sine wave time = 0.64ms -15 -13 -11 -9 -7 -5 -3 -1 1 10 100 1k 10k 100k frequency (hz) gain (db) primary v bus primary v shunt time = 0.64ms 0 1 2 3 4 5 6 7 8 9 10 -20 -15 -10 -5 0 5 10 15 20 v os (mv) hits v input = 25mv -20 -15 -10 -5 0 5 10 15 20 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) v os (mv) t = +125c v input = 25mv t = +25c t = -40c isl28023 15 fn8389.4 june 17, 2015 submit document feedback figure 21. primary v bus v os tc figure 22. primary v bus v os vs temperature figure 23. primary v bus adc gain error fig ure 24. primary v bus adc gain error tc figure 25. primary v bus measurement error vs input figure 26. primary v bus measurement error vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 2 4 6 8 10 12 -100 -75 -50 -25 0 25 50 75 100 v os tc (v/c) hits v input = 25mv -20 -15 -10 -5 0 5 10 15 20 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) v os (mv) v cc = 5v v cc = 3v v input = 25mv v cc = 3.3v 0 1 2 3 4 5 6 7 8 -0.20 -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 gain error (%) hits isl28023-12 (1v to 16v) isl28023-60 (12v to 60v) 0 1 2 3 4 5 6 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 gain error tc (ppm/c) hits isl28023-12 (1v to 16v) isl28023-60 (12v to 60v) -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0 8 16243240485664 v input (v) measurement error (%) v cc (12) = 5v v cc (12) = 3v v cc (12) = 3.3v v cc (60) = 3v v cc (60) = 5v v cc (60) = 3.3v -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) measurement error (%) v cc (12) = 5v v cc (12) = 3v v cc (12) = 3.3v v cc (60) = 5v v cc (60) = 3v v cc (60) = 3.3v isl28023 16 fn8389.4 june 17, 2015 submit document feedback figure 27. auxiliary v shunt v os figure 28. auxiliary v shunt v os vs v cc figure 29. auxiliary v shunt v os tc (-40c to +125c) figure 30. auxiliary v shunt v os vs temperature figure 31. auxiliary v shunt cmrr, cmv = (0v to 3.3v) figure 32. auxiliary v shunt cmrr vs temperature (cmv = 0v to 3.3v) typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 2 4 6 8 10 12 14 -30.0 -22.5 -15.0 -7.5 0 7.5 15.0 22.5 30.0 v os (v) hits -50 -40 -30 -20 -10 0 10 20 30 40 50 3 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) v os (v) t = -40c t = +25c t = +125c 0 2 4 6 8 10 12 -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0.075 0.100 v os tc (v/c) hits -40 -30 -20 -10 0 10 20 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) v os (v) v cc = 5v v cc = 3v v cc = 3.3v 0 1 2 3 4 5 6 7 -7.00 -5.25 -3.50 -1.75 0 1.75 3.50 5.25 7.00 cmrr (v/v) hits -7 -5 -3 -1 1 3 5 7 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) cmrr (v/v) isl28023 17 fn8389.4 june 17, 2015 submit document feedback figure 33. auxiliary v shunt v os vs cmv figure 34. auxiliary v shunt common mode range figure 35. auxiliary v shunt adc gain error figure 36. auxiliary v shunt adc gain error tc figure 37. auxiliary v shunt measurement error vs input figure 38. auxiliary v shunt measurement error vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -20 -15 -10 -5 0 5 10 15 20 0 0.51.01.52.02.53.03.54.04.55.05.56.0 cmv (v) v os (v) v cc = 6v 35 45 55 65 75 85 95 -80 -70 -60 -50 -40 -30 -20 -10 0 cmv (mv) v meas (mv p-p ) v input = 80mv p-p sine wave to cmv = v cc frequency = 100hz adc timing = 64s 0 1 2 3 4 5 6 -0.10 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0.00 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 v auxshunt measurement error (%) hits 0 1 2 3 4 5 6 7 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 v auxshunt gain error (ppm/c) hits -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06 0.08 v input (v) measurement error (%) v cc = 5v v cc = 3.3v v cc = 3v -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) measurement error (%) v cc = 5v v cc = 3v v cc = 3.3v isl28023 18 fn8389.4 june 17, 2015 submit document feedback figure 39. auxiliary v bus bandwidth vs adc timing figure 40. auxiliary v shunt and v bus vs frequency figure 41. auxiliary v bus v os figure 42. auxiliary v bus v os vs v cc figure 43. auxiliary v bus v os tc figure 44. auxiliary v bus vos vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -15 -13 -11 -9 -7 -5 -3 -1 1 10 100 1k 10k 100k frequency (hz) gain (db) time = 0.256ms time = 0.128ms time = 0.64ms time = 2.048ms time = 1.024ms time = 0.512ms -15 -13 -11 -9 -7 -5 -3 -1 1 10 100 1k 10k 100k frequency (hz) gain (db) aux v bus aux v shunt time = 0.64ms 0 2 4 6 8 10 12 -5.00 -3.75 -2.50 -1.25 0 1.25 2.50 3.75 5.00 v os (mv) hits v input = 25mv -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) v os (mv) t = -40c t = +125c t = +25c v input = 25mv 0 2 4 6 8 10 12 -20 -15 -10 -5 0 5 10 15 20 v os tc (v/c) hits v input = 25mv -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) v os (mv) v cc = 3.3v v cc = 5v v cc = 3v v input = 25mv isl28023 19 fn8389.4 june 17, 2015 submit document feedback figure 45. auxiliary v bus adc gain error figure 46. auxiliary v bus adc gain error tc figure 47. auxiliary v bus measurement error vs in put figure 48. auxiliary v bus measurement error vs temperature figure 49. internal temperature ac curacy at t = +25c figure 50. intern al temperature sensor accuracy typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -0.20 -0.18 -0.16 -0.14 -0.12 -0.10 -0.08 -0.06 -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 gain error (%) hits 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 v auxshunt gain error tc (ppm/c) hits -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 0.51.01.52.02.53.03.54.04.55.05.5 aux v (v) measurement error (%) v cc = 5v v cc = 3v v cc = 3.3v -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) measurement error (%) v cc = 5v v cc = 3v v cc = 3.3v 0 2 4 6 8 10 12 14 16 -3.500 -2.625 -1.750 -0.875 0 0.875 1.750 2.625 3.500 ? temperature (c) hits -3.5 -2.5 -1.5 -0.5 0.5 1.5 2.5 3.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) ? temperature (c) v cc = 5v v cc = 3v v cc = 3.3v t eqn_3.3 = -5.286*10 -11 * t meas 5 + 7.458 * 10 -9 * t meas 4 - 1.712 * 10 -6 * t meas 3 + 1.996 * 10 -4 * t meas 2 - 1.01 * t meas 1 + 0.813 isl28023 20 fn8389.4 june 17, 2015 submit document feedback figure 51. internal temperature ac curacy at t = -40c figure 52. inte rnal temperature accuracy vs v cc figure 53. internal temperature accu racy at t = +85c figure 54. internal temperature accuracy at t = +125c figure 55. supply current vs te mperature figure 56. power-down su pply current vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 1 2 3 4 5 6 7 8 9 -3.500 -2.625 -1.750 -0.875 0 0.875 1.750 2.625 3.500 ? temperature (c) hits -5 -4 -3 -2 -1 0 1 2 3 4 5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) ? temperature (c) t = +125c t = -40c t = +25c 0 1 2 3 4 5 6 7 8 9 -3.500 -2.625 -1.750 -0.875 0 0.875 1.750 2.625 3.500 ? temperature (c) hits 0 1 2 3 4 5 6 -3.500 -2.625 -1.750 -0.875 0 0.875 1.750 2.625 3.500 ? temperature (c) hits 0 200 400 600 800 1000 1200 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) supply current (a) mode = nmrl+oc mode = nmrl+dacoen mode = nmrl+ov mode = nmrl+dacen mode = nmrl mode = nmrl+uv 0 10 20 30 40 50 60 70 80 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) supply current (a) mode = adc pd, mode = pd isl28023 21 fn8389.4 june 17, 2015 submit document feedback figure 57. supply current vs supply voltage figure 58. supply current vs supply voltage (power-down modes) figure 59. primary v shunt bias current vs temper ature figure 60. primary v shunt bias current vs temperature (power-down mode) figure 61. primary v shunt bias current offset vs temperature figure 62. primary v shunt bias current offset vs temperature (power-down mode) typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 200 400 600 800 1000 1200 3.0 3.5 4.0 4.5 5.0 5.5 6.0 temperature (c) supply current (a) mode = nmrl+oc mode = nmrl+dacoen mode = nmrl+uv mode = nmrl+ov mode = nmrl+dacen mode = nmrl 0 1 2 3 4 5 6 7 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) supply current (a) mode = adc pd, mode = pd -9.8 -9.6 -9.4 -9.2 -9.0 -8.8 -8.6 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) bias current (a) mode = nmrl+oc mode = nmrl -0.30 -0.25 -0.20 -0.15 -0.10 -0.05 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) bias current (a) mode = pd, mode = adcpd -140 -120 -100 -80 -60 -40 -20 0 20 40 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) offset current (na) mode = nmrl+oc mode = nmrl -35 -30 -25 -20 -15 -10 -5 0 5 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) offset current (na) mode = pd mode = adcpd isl28023 22 fn8389.4 june 17, 2015 submit document feedback figure 63. primary v shunt bias current vs common mode voltage figure 64. primary v shunt bias current vs common mode voltage (power-down modes) figure 65. primary v shunt offset current vs common mode voltage figure 66. primary v shunt offset current vs common mode voltage (power-down modes) figure 67. auxiliary v shunt bias current vs temper ature figure 68. auxiliary v shunt bias current offset vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -12 -10 -8 -6 -4 -2 0 0 8 16 24 32 40 48 56 64 cmv (v) bias current (a) mode = nmrl+oc mode = nmrl -0.007 -0.006 -0.005 -0.004 -0.003 -0.002 -0.001 0 0.001 0 8 16 24 32 40 48 56 64 cmv (v) bias current (a) mode = pd mode = adc pd -40 -35 -30 -25 -20 -15 -10 -5 0 5 0 8 16 24 32 40 48 56 64 cmv (v) offset current (na) mode = nmrl+oc mode = nmrl -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 8 16 24 32 40 48 56 64 cmv (v) offset current (na) mode = pd mode = adc pd -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) bias current (a) v cc = 6v v cm = 3.3v mode = nmrl mode = adcpd -20 -15 -10 -5 0 5 10 15 20 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) offset current (na) v cc = 6v v cm = 3.3v mode = adcpd mode = nmrl isl28023 23 fn8389.4 june 17, 2015 submit document feedback figure 69. auxiliary v shunt power down bias current vs temperature figure 70. auxiliary v shunt power down bias current offset vs temperature figure 71. auxiliary v shunt bias current vs common mode voltage figure 72. auxiliary v shunt bias current offset vs common mode voltage figure 73. auxiliary v shunt power down bias current vs common mode voltage figure 74. auxiliary v shunt power down bias current offset vs common mode voltage typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -0.25 -0.20 -0.15 -0.10 -0.05 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) bias current (a) v cc = 6v v cm = 3.3v 0 0.02 0.04 0.06 0.08 0.10 0.12 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) offset current (na) v cc = 6v v cm = 3.3v -6 -5 -4 -3 -2 -1 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cm (v) bias current (a) v cc = 6v mode = nmrl mode = adcpd -25 -20 -15 -10 -5 0 5 10 15 20 25 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cm (v) offset current (na) v cc = 6v mode = nmrl mode = adcpd -0.0020 -0.0018 -0.0016 -0.0014 -0.0012 -0.0010 -0.0008 -0.0006 -0.0004 -0.0002 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cm (v) bias current (a) v cc = 6v 0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cm (v) offset current (na) v cc = 6v isl28023 24 fn8389.4 june 17, 2015 submit document feedback figure 75. v reg output voltage distribution figure 76. v reg output vs temperature figure 77. v reg output vs input voltage figure 78. v reg output vs current load figure 79. v reg input current vs input voltage figure 80. v reg input current vs temperature typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 1 2 3 4 5 6 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 3.28 3.29 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.37 3.38 3.39 3.40 v reg (v) hits 3.20 3.25 3.30 3.35 3.40 3.45 3.50 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) v reg output (v) i load = 6ma i load = 3ma i load = 0ma 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 0 8 16 24 32 40 48 56 64 v reg input (v) v reg output (v) -25 -20 -15 -10 -5 0 0.1 1 10 100 i load (ma) v reg change (mv) 2 3 4 5 6 7 8 0 8 16 24 32 40 48 56 64 v reg input voltage (v) i reg (a) 2 3 4 5 6 7 8 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) i reg (a) isl28023 25 fn8389.4 june 17, 2015 submit document feedback figure 81. margin dac vs v cc figure 82. normalized dac output vs temperature figure 83. margin dac vs current load figure 84. margin dac dnl figure 85. margin dac inl per code figure 86. ov or uv or oc alert response time typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v cc (v) normalized dac output (%) -0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 -60 -40 -20 0 20 40 60 80 100 120 140 160 temperature (c) normalized dac output (%) 0 20 40 60 80 100 120 140 160 180 200 0.1 1 10 current load (ma) abs (dac output change) (mv) dac out sink dac out source -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 code dnl (lsb) -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0 20 40 60 80 100 120 140 160 180 200 220 240 260 code inl (lsb) -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 time (s) input smbalert isl28023 26 fn8389.4 june 17, 2015 submit document feedback figure 87. primary shunt stability: stdev vs acquisition time figure 88. primary shunt stability: range vs acquisition time figure 89. primary shunt stab ility: stdev vs internal averaging figure 90. primary shunt stability: range vs internal averaging figure 91. auxiliary shunt stability: stdev vs acquisition time figure 92. auxiliary shunt stability: range vs acquisition time typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 10 20 30 40 50 60 70 80 50 250 450 650 850 1050 1250 1450 1650 1850 2050 adc timing (s) sigma of measurement (v) sample size = 1024 0 50 100 150 200 250 300 350 400 450 500 50 250 450 650 850 1050 1250 1450 1650 1850 2050 adc timing (s) range of meas urement (v) sample size = 1024 0 2 4 6 8 10 12 0 40 80 120 160 200 240 280 320 360 400 440 480 520 internal averaging sigma of measurement (v) sample size = 1024 adc timing = 2.048ms 0 5 10 15 20 25 30 35 0 40 80 120 160 200 240 280 320 360 400 440 480 520 internal averaging range of measurement (v) sample size = 1024 adc timing = 2.048ms 0 10 20 30 40 50 60 70 80 50 250 450 650 850 1050 1250 1450 1650 1850 2050 adc timing (s) sigma of measurement (v) sample size = 1024 0 50 100 150 200 250 300 350 400 450 500 50 250 450 650 850 1050 1250 1450 1650 1850 2050 adc timing (s) range of measurement (v) sample size = 1024 isl28023 27 fn8389.4 june 17, 2015 submit document feedback overview the isl28023 is a digital current , voltage and power monitoring device for high and low-side power monitoring in positive and negative voltage applications. the digital power monitor (dpm) requires an external shunt resistor to enable current measurements. the shunt resistor translates the bus current to a voltage. the dpm measures the voltage across the shunt resist ors and reports the measured value out digitally via an i 2 c interface. a register within the dpm is reserved to store the value of the shunt resistor. the stored current sense resistor value allows the dpm to output a current value to an external digital device. the isl28023 has two channels which allow the user to monitor the voltage, current and power on two power supply rails. the two channels for the dpm consist of a primary channel and an auxiliary channel. the primary channel will allow and measure voltages from 0v to 60v or from 0v to 16.384v, depending on the option of the isl28023. the auxiliary channel can tolerate and measure voltage from 0v to v cc . the isl28023 has continuous fa ult detection for the primary channel. the dpm can be configured to set an alert in the instance of an overvoltage, un dervoltage and/or overcurrent event. the response ti me of the alert is 500ns from the event. the isl28023 has a temperature sensor with fault detection. an 8-bit margin dac, controllable through i 2 c communication, is incorporated into the dpm. the voltage margining feature allows for the adjustment of the regulated voltage to the load. the margin dac can help in proving the load robustness versus the applied supply voltage. the isl28023 offers a 3.3v voltage regulator that can be used to power the chip in addition to low power peripheral circuitry. the dpm has an i 2 c power pin that allows the i 2 c master to set the digital communication supply volt age to the chip. the operating supply voltage for the dpm ranges from 3v to 5.5v. the device will accept i 2 c supply voltages between 1.2v and 5.5v. the isl28023 accepts smbus protocols up to 3.4mhz. the device is pmbus compliant up to 400mhz. the device has packet error code (pec) functionality. the pec protocol uses an 8-bit cyclic redundance check (crc-8) represented by the polynomial x 8 +x 2 +x 1 +1. the isl28023 can be configured for up to 55 unique slave addresses using 3 address select bits. the large amount of addressing allows 55 parts to communicate on a single i 2 c bus. it also gives the designer the flexibility to select a unique address when another sl ave address conflicts with the dpm on the same i 2 c bus. pin descriptions vbus vbus is the power bus voltage input pin. the pin should be connected to the desired power supply bus to be monitored. the voltage range for the pin is from 0v to 60v or 0v to 16v depending on the isl28023 version. vinp vinp is the shunt voltage monitor positive input pin. the pin connects to the most positive voltage of the current shunt resistor. the voltage range for the pin is from 0v to 60v or 0v to 16v depending on the isl2 8023 version. the maximum measurable voltage differential between vinp and vinm is 80mv. vinm vinm is the shunt voltage monitor negative input pin. the pin connects to the most negative volt age of the current shunt resistor. the voltage range for the pin is from 0v to 60v or 0v to 16v depending on the isl28023 version. the maximum measurable voltage differential between vinp and vinm is 80mv. auxv auxv is the power bus voltage input pin. the pin should be connected to the desired power supply bus to be monitored. the voltage range for the pin is from 0v to v cc . figure 93. auxiliary shunt stability: stdev vs internal averaging figure 94. auxiliary shunt stability: range vs internal averaging typical performance curves t a = +25c, v cc = 3.3v, v inp = v bus = 12v, auxp = auxv = 3v, v shunt =v auxshunt = 80mv, conversion time: aux = primary = 2.05ms, internal avg aux = primary = 128 ; unless otherwise specified. (continued) 0 1 2 3 4 5 6 7 8 0 40 80 120 160 200 240 280 320 360 400 440 480 520 internal averaging sigma of measurement (v) sample size = 1024 adc timing = 2.048ms 0 5 10 15 20 25 0 40 80 120 160 200 240 280 320 360 400 440 480 520 internal averaging range of measurement (v) sample size = 1024 adc timing = 2.048ms isl28023 28 fn8389.4 june 17, 2015 submit document feedback auxp auxp is the auxiliary shunt voltage monitor positive input pin. the pin connects to the most po sitive voltage of the auxiliary current shunt resistor. the voltage range for the pin is from 0v to v cc . the maximum measurable vo ltage differential between auxp and auxm is 80mv. auxm auxm is the auxiliary shunt volt age monitor negative input pin. the pin connects to the most negative voltage of the auxiliary current shunt resistor. the voltage range for the pin is from 0v to v cc . the maximum measurable vo ltage differential between auxp and auxm is 80mv. vcc vcc is the positive supply voltage pin. vcc is an analog power pin. vcc supplies power to the device. the allowable voltage range is from 3v to 5.5v. i2cvcc i2cvcc is the positive supply vo ltage pin. i2cvcc is an analog power pin. i2cvcc supplies power to the digital communication circuitry, i 2 c, of the device. the allowable voltage range is from 1.2v to 5.5v. gnd device ground. for single supply systems, the pin connects to system ground. for dual supply systems, the pin connects to the negative voltage supply in the system. vreg_in vreg_in is the voltage regulator input pin. the operable input voltage range to the regulator is 4.5v to 60v. vreg_out vreg_out is the voltage regulator output pin. the regulated output voltage of 3.3v is sourced from the vreg_out pin. dac_out dac_out is the margin dac output pin. the output of the dac voltage ranges from 0v to 2.4v. the voltage dac is controlled through internal registers. address pins (a0, a1, a2) a0, a1 and a2 are address select able pins. the address pins are i 2 c/smbus slave address select pins that are multilogic programmable for a total of 55 different address combinations. there are four selectable levels for the address pins, i2cvcc, gnd, scl/smbclk, and sda/smbdat. see table 49 for more details in setting the slave address of the device. smbdat sda/smbdat is the serial data input/output pin. sda/smbdat is a bidirectional pin used to tran sfer data to and from the device. the pin is an open drain output and may be wired with other open drain/collector outputs. the input buffer is always active (not gated). the open drain output requires a pull-up resistor for proper functionality. the pull-up resistor should be connected to i2cvcc of the device. smbclk scl/smbclk is the serial cloc k input pin. the scl/smbclk input is responsible for clocking in all data to and from the device. the input buffer on the pin is always active (not gated). the input pin requires a pull-up resistor to i2cvcc of the device. smbalert pins (smbalert1, smbalert2) the smbalert pins are output pins. the smbalert1 is an open drain output and requires a pull-up resistor to a power supply up to 24v. the smbalert2 has a push/pull output stage. the smbalert pins are fault acknowledgment pins. the pin can be connected to peripheral circuitry to halt operations when a fault event occurs. extclk ext_clk is the external clock pin. ext_clk is an input pin. the pin provides a connection to the system clock. the system clock is connected to the adc. the acquisitions rate of the adc can be varied through the ext_clk pin. the pin functionality is set through a control register bit. table 2. isl28023 register descriptions register address (hex) register name function power on reset value (hex) number of bytes access type page ic device details 19 capability pmbus supportability b0 1 r 31 20 vout_mode describes the adc read back format 40 1 r 31 99 pmbus_rev pmbus revision 22 1 r 31 ad ic_device_id device id 49534c3238303233 8 r 31 ae ic_device_rev device revision and silicon version 000002 3 r 31 global ic controls 12 restore_default_all soft reset n/a 0 w 32 01 operation turns the device on and off 80 1 r/w 32 isl28023 29 fn8389.4 june 17, 2015 submit document feedback primary and auxiliary channel controls d2 set_dpm_mode configures the isl28023 0a 1 r/w 32 d3 dpm_conv_status indicates the status of a conversion n/a 1 r 32 d4 config_ichannel shunt inpu ts (primary and auxiliary) configuration 0387 2 r/w 33 38 iout_cal_gain calibration that enables primary current measurements 0000 2 r/w 33 d5 config_vchannel bus inputs (primary and auxiliary) configuration 0387 2 r/w 34 d7 config_peak_det enables primary channel current peak detector 00 1 r/w 34 e2 config_excitation enables temp measurem ents on the auxiliary shunt input 00 1 r/w 34 measurement registers d6 read_vshunt_out primary shunt measurement value 0000 2 r 35 8b read_vout primary bus measurement value 0000 2 r 35 8c read_iout primary current measurement value 0000 2 r 35 d8 read_peak_min_iout primary current max measurement value 7fff 2 r 35 d9 read_peak_max_iout primary current min measurement value 8001 2 r 35 96 read_pout primary power measurement value 0000 2 r 35 e0 read_vshunt_out_aux axillary shunt measurement value 0000 2 r 36 e1 read_vout_aux auxiliary bus measurement value 0000 2 r 36 8d read_temperature_1 internal te mperature measurement value 0000 2 r 36 threshold detectors da vout_ov_threshold_set overvoltage/over- temperature threshold configuration 003f 2 r/w 36 db vout_uv_threshold_set undervoltage threshold configuration 00 1 r/w 37 dc iout_oc_threshol d_set overcurrent threshold configuration 003f 2 r/w 37 smb alert dd config_intr configure the behavior of the interrupts 0000 2 r/w 39 de force_feedthr_alert configure the path of the interrupt signal 00 1 r/w 40 1b smbalert_mask alert mask fo r the smbalert1 pin n/a 2 r/w 41 df smbalert2_mask alert mask for the smbalert2 pin n/a 1 r/w 41 03 clear_faults clears all faults n/a 0 w 40 7a status_vout alert bits related to the primary bus 00 1 r/w 40 7b status_iout alert bit related to the primary shunt 00 1 r/w 40 7d status_temperature alert bit related to temperature 00 1 r/w 40 7e status_cml alert bits related to communication errors 00 1 r/w 41 78 status_byte alert bits related to temperature and device status 00 1 r/w 41 79 status_word alert bits related to all primary inputs 0000 2 r/w 41 voltage margin e4 config_vol_margin configures the margin dac 00 1 r/w 43 e3 set_vol_margin value to load into the margin dac 80 1 r/w 43 external clock control e5 config_ext_clk configures external cl ock; enable/disable smbalert2 00 1 r/w 42 table 2. isl28023 register descriptions (continued) register address (hex) register name function power on reset value (hex) number of bytes access type page isl28023 30 fn8389.4 june 17, 2015 submit document feedback communication protocol the dpm chip communicates with the host using pmbus commands. pmbus command structure is an industry smbus standard for communicating with power supplies and converters. all communications to and from the chip use the smbclk and smbdat to communicate to the dpm master. the smb pins require a pull-up resistor to enable proper operation. the default logic state of the communication pi ns are high when the bus is in an idle state. the smbus standard is a variant of the i 2 c communication standard with minor differences with timing and dc parameters. smbus supports packet error corrections (pec) for data integrity certainty. the pmbus is the standardization of the smbus register designation. the standardization is specific to power and converter devices. the dpm employs the following command structures from the i 2 c communication standard; 1. send byte 2. write byte/word 3. read byte/word 4. read block 5. write block packet error correction (pec) packet error correction is often used in environments where data being transferred to and from the device can be compromised. applications where the device is connected by way of a cable is common use of pec. the cable?s integrity may be compromised resulting in error transactions between the master and the device. the isl28023 uses an 8- bit cyclic redundance check (crc-8). figure 95 is an example of a flow algorithm for crc-8 protocol. figure 95. an algorithm to calc ulate a crc8 (pec) byte value. public function crc8decode(binstr as string) as byte declaration of variables dim crc8(0 to 7) as byte, index as byte, doinvert as byte the input to the subroutine is a binary string consisting of the slave address, the register address and data inputted to or received from the part. anything input into or received from the device is part of the binary string (binstr) to be calculated by this routine. clear the crc8 variable. this variable is used to return the pec value. for index = 0 to ubound(crc8) crc8(index) = 0 next index index = 0 while index <> (len(binstr)) index = index + 1 the if statement below reads the binary value of each bit in the binary string (binstr). if mid(binstr, index, 1) = "1" then doinvert = 1 xor crc8(7) else doinvert = 0 xor crc8(7) end if crc8(7) = crc8(6) crc8(6) = crc8(5) crc8(5) = crc8(4) crc8(4) = crc8(3) crc8(3) = crc8(2) crc8(2) = crc8(1) xor doinvert crc8(1) = crc8(0) xor doinvert crc8(0) = doinvert wend crc8decode = 0 for index = 0 to 7 ' this assembles the crc8 value in byte form. crc8decode = crc8(index) * 2 ^ index + crc8decode next index ? crc8decode is returned from this routine. end function figure 96. read/write smbus prot ocols with and without pec. diagrams copied from a smbus specification document. the document can be uploaded at http://smbus.org/specs/ isl28023 31 fn8389.4 june 17, 2015 submit document feedback ic device details 0x19 capability (r) the capability register is a read on ly byte register that describes the supporting communication standard by the dpm chip. the dpm chip supports packet error correction (pec) protocol. the maximum pmbus bus speed that the dpm supports is 400khz. the dpm supports a higher speed option that is not compliant to the pmbus standard. the higher speed option is discussed later in the datasheet. the dpm chip has smb alert pins which supports smb alert commands. 0x20 v out mode (r) the v out mode register is a readable byte register that describes the method to calculate read back values from the dpm such as voltage, current, power and temperature. the value for the register is 0x40. the register value represents a direct data read back format. for unsigned registers such as v bus , the register value is calculated using equation 1 . otherwise, equation 2 is used for signed readings. n is the bit position within the re gister value. bit_val is the value of the bit either 1 or 0. 0x99 pmbus rev (r) the pmbus rev register is a readab le byte register that describes the pmbus revision that the dpm is compliant to. pmbus rev part 1 is a pmbus specification pertaining to electrical transactions and hardware interface. pmbus rev part 2 specification pertains to the command calls used to address the dpm. a nibble of 0000 translates to revision 1.0 of either pmbus revision. a nibble of 0001 equals 1.1 of either pmbus revision. 0xad ic device id (br) the ic device id is a block read able register that reports the device product name being addressed. the product id that is stored in the register is ?isl28023?. each character is stored as an ascii number. a 0x30 equals ascii ?0?. a 0x49 translates to an ascii ?i?. figure 97 illustrates the convention for performing a block read. 0xae ic_device_rev (br) the ic device revision is a bloc k readable register that reports back the revision number of th e silicon and the version of the silicon. the register is 3 bytes in length. silicon version d[11] data bit11 of the ic revision register reports the version of the silicon. table 3. 0x19 capability register definition bit number d7 d[6:5] d4 d[3:0] bit name pec max bus speed smb alert support n/a default value 1 01 1 0000 (eq. 1) register value 0 15 n bit_val n 2 n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? (eq. 2) register value 0 14 n bit_val n 2 n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit_val 15 2 15 ? ? ? ? ? ? table 4. 0x99 pmbus rev register definition bit number d[7:4] d[3:0] bit name pmbus rev part i pmbus rev part ii default value 0010 0010 table 5. 0xae ic device rev register definition bit number d[23:12] d[11] d[10:0] bit name n/a silicon version silicon revision default value 0000 0011 0000 1 000 0000 0010 table 6. d[11] silicon version bit defined d16 status 0 60v 1 12v figure 97. block read smbus protocols wi th and without pec. diagrams copied from smbus specification document. the document can be uploaded at http://smbus.org/specs/ isl28023 32 fn8389.4 june 17, 2015 submit document feedback global ic controls 0x12 reset default all (s) the restore default all register is a send byte command that restores all registers to th e default state defined in table 2 . 0x01 operation (r/w) the operation register is a read writable byte register that controls the overall power up stat e of the chip. data bit 7 of the register configures the power stat us of the chip. the power status is defined in table 7 . yellow shading in the table is the default setting of the bit at power-up. primary and auxiliary channel controls 0xd2 set dpm mode (r/w) the set dpm mode is a read writab le byte register that controls the data acquisition behavior of the chip. adc enable d[6] data bit 6 of the set dpm mode register controls the adc power state within the dpm chip. at power-up, the adc is powered up and is available to take data. adc state d[5] data bit5 of the set dpm mode register controls the adc state. the idle state of the adc does not acquire data from any input of the dpm. normal operating mode has the adc acquiring data in a systematic way. post trigger state d[4] data bit 4 of the set dpm mode register controls the post adc state once an acquisition has be en made in the trigger mode. adc mode type d[3] data bit 3 of the set dpm mode re gister controls the behavior of the adc to either triggered or continuous. the continuous mode has the adc continuously acquir ing dat in a systematic manor described by data bits[2:0] in the set dpm mode register. the triggered mode instructs the adc to make an acquisition described by data bits[2:0]. th e beginning of a triggered cycle starts once writing to the set dpm mode register commences. the trigger mode is useful for reading a single measurement per acquisition cycle. operating mode d[2:0] the operating mode bits of the se t dpm mode register controls the state machine within the chip. the state machine globally controls the overall functionality of the chip. table 13 shows the various measurement states the chip can be configured to, as well as the mode bit definitions to achieve a desired measurement state. the shaded row is the default setting upon power-up. 0xd3 dpm conversion status (r) the dpm conversion status register is a readable byte register that reports the status of a conversion when the dpm is programmed in the trigger mode. table 7. 0x01 operation register bit7 defined d7 status 0 power-down 1 normal operation table 8. 0xd2 set dpm mo de register definition bit number d[7] d6 d[5] d[4] d[3] d[2:0] bit name n/a adc enable adc state post trigger state adc mode type operating mode default value00001010 table 9. 0xd2 set dpm mode register bit6 defined d6 adc pd 0 normal mode 1 adc powered down table 10. 0xd2 set dpm mode register bit5 defined d5 adc state 0 normal state 1 adc in idle state table 11. 0xd2 set dpm mode register bit4 defined d4 post trigger state 0 idle mode after a trigger measurement 1 pd mode after trigger measurement table 12. 0xd2 set dpm mode register bit3 defined d3 adc mode type 0 trigger 1 continuous table 13. 0xd2 set dpm mode re gister bits 2 to 0 defined d[2:0] measurement input 0 primary channel shunt voltage 1 primary channel v bus voltage 2 primary shunt and v bus voltages 3 auxiliary channel shunt voltage 4 auxiliary channel v bus voltage 5 auxiliary shunt and v bus voltages 6 internal temperature 7 all table 14. 0xd3 dpm conversion status register definition bit number d[7:2] d[1] d[0] bit name n/a cnvr ovf default value 0 0 0 isl28023 33 fn8389.4 june 17, 2015 submit document feedback cnvr: conversion ready d[1] the conversion ready bit indicates when the adc has finished a conversion and has transferred the reading(s) to the appropriate register(s). the cnvr is only operable when the adc state is set to trigger. the cnvr is in a high state when the conversion is in progress. when the cnvr bit tran sitions from a high state to a low state and remains at a low state, the conversion is complete. the cnvr initializes or reinitializes when writing to the set dpm mode register. ovf: math overflow flag d[0] the math overflow flag (ovf) bit is set to indicate the current and power data being read from the dpm is overranged and meaningless. 0xd4 configure ichannel (r/w) the configure ichannel register is a read/writable word register that configures the adc measurement acquisition settings for the primary and auxiliary voltage shunt inputs. shunt voltage conversion time d[9:7], d[2:0] the shunt voltage conversion time bits set the acquisition speed of the adc when measuring either the primary or auxiliary voltage shunt channels of the dpm. the primary and auxiliary v shunt channels have independent ti ming control bits allowing for the primary v shunt channel to have a unique acquisition time with respect to the auxiliary v shunt channel. table 16 is a list of the selectable v shunt adc time settings. the shaded row indicates the default setting. shunt voltage sample average d[13:10], d[6:3] the shunt voltage sample average bits set the number of averaging samples for a unique sampling time. the dpm will record all samples and output the average resultant to the respective v shunt register. the primary and auxiliary v shunt channels have independent average settings allowing for the primary v shunt channel to have a unique average setting with respect to the auxiliary average setting. table 17 defines the list of selectable averages the dpm can be set to. the shaded row indicates the default setting. 0x38 iout calibration gain (r/w) the iout calibration gain register is a read/writable word register that is used to calculate current and power measurements for the primary channel of the dpm. when the register is programmed, the dpm calculates the current and power based on the primary channels v bus and v shunt measurements. the calculation resultant is stored in the read_iout and read_pout registers. the calibration register value can be calculated as follows: 1. calculate the full-scale current range that is desired. this can be calculated using equation 3 . 2. r shunt is the value of the shunt resistor. vshunt fs is the full-scale range of the primary channel, which equals 80mv. 3. from the current full-scale range, the current lsb can be calculated using equation 4 . current full-scale is the outcome from equation 3 . adc res is the resolution of shunt voltage reading. the output of the ad c is a signed 15-bit binary number. therefore, the adc res value equals 2 15 or 32768. 4. from equation 4 , the calibration resistor value can be calculated using equation 5 . the resolution of the math that is processed internally in the dpm is 2048 or 11 bits of resolution. the v shunt lsb is set to 2.5v. equation 5 yields a 15-bit binary number that can be written to the calibration register. the calibration register format is represented in table 18 . table 15. 0xd4 configure ichannel register definition bit number d[15:14] d[13:10] d[9:7] d[6:3] d[2:0] bit name n/a aux shunt sample avg aux shunt conversion time prim shunt sample avg prim shunt conversion time default value 00 00 00 11 1 000 0 111 table 16. auxiliary/ primary v shunt conversion times defined config_ichannel: d[9:7],d[2:0] conversion time 0 0 0 64s 0 0 1 128s 0 1 0 256s 0 1 1 512s 10 x 1.024ms 1 1 x 2.048ms table 17. auxiliary/ primary v shunt number of samples to average defined avg[3:0] converter averages 0 0 0 0 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 512 1010 1024 1 0 1 1 2048 1 1 x x 4096 (eq. 3) current fs vshunt fs r shunt current lsb current fs adc res isl28023 34 fn8389.4 june 17, 2015 submit document feedback 0xd5 configure vchannel (r/w) the configure vchannel register is a read/writable word register that configures the adc measurement acquisition settings for the primary and auxiliary voltage bus inputs. the adc configuration of the sampling average and conversion time settings for v bus and auxv channels have the same setting choices as the v shunt primary and auxiliary channels. 0xd7 configure peak detector (r/w) the configure peak detector regi ster is a read/writable byte register that toggles the minimum and maximum current tracking feature. a peak detect enable bit setting of 1 enables the current peak detect feature of the dpm. the feature is discussed in more detail in ? 0xd8 read peak min i out (r) ? on page 35 . 0xe2 configure excitation (r/w) the configure excitation register is a read/writable byte register that changes the measurement fu nctionality of the auxiliary v shunt input. the default state of the register configures the auxiliary v shunt input to measure the differential voltage across the auxp and auxm inputs. the maximum meas urable voltage that can be applied to the inputs is 80mv. setting the ext temp en bit to 1 activates the current sourcing circuitry at the auxiliary v shunt input. connecting a diode between auxp and auxm will enable external temperature measurement functionality. the external temperature measurement mode forces two currents (20a/100a) through the diode. the differential voltage between the auxp and auxm pins for each current forced are measured and stored by way of a sample and hold circuitry. the timing for the two current measurement is 1s. the maximum voltage that can be me asured between the auxiliary vshunt pins is vcc. upon completion of the two current measurements, the adc measures the difference between the two stored differential voltage values. the measured value by the adc yields the ? vbe voltage for the two currents. the maximum ? vbe voltage that the temperature circuit can measure is 80mv. the dpm stores the measured value from the adc in the read_temperature_1 register. using equation 2 to calculate the register signed integer value, the ? vbe voltage can be calculated using equation 6 . register value is the read_temperature_1 signed integer value. the aux_vshunt lsb equals 10v. equation 7 yields the absolute temperature from the current measurements. table 18. 0x38 iout_cal_gain definition bit number d[15] d[14:0] bit name n/a iout_cal_gain default value 0 000 0000 0000 0000 table 19. 0xd5 configure vchannel register definition bit number d[15:14] d[13:10] d[9:7] d[6:3] d[2:0] bit name n/a auxv sample avg auxv conversion time v bus sample avg v bus conversion time default value 00 00 00 11 1 000 0 111 table 20. 0xd7 configure peak detector register definition bit number d[7:1] d[0] bit name n/a peak detect en default value 0000 000 0 table 21. 0xe2 configure excitation register definition bit number d[15:1] d[0] bit name n/a ext temp en default value 0000 0000 0000 000 0 (eq. 5) calreg val integer math res vshunt lsb ? current lsb r shunt ? ?? ? ? ? ? ? ? calreg val integer 0.00512 current lsb r shunt ? ?? ? ? ? ? ? ? figure 98. simplified circuit diagram of an external temperature application i2c sm bus pm bus a0 a1 smbclk smbdat vinp vinm vbus adc 16-bit vbus_vsense auxp auxm to c aux_vsense cm = 0 to 60v cm = 0 to vcc a2 auxv 20a and/or 100a sw mux ext_temp_en (eq. 6) ? vbe register value aux_vshunt lsb ? (eq. 7) t q nk ? ? ? ? ? ? ? ? vbe ln i 2 i 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 273 ? isl28023 35 fn8389.4 june 17, 2015 submit document feedback the ? vbe value calculated in equation 6 is used to calculate the temperature in centigrade (c). the value of the two currents that are sourced from the part during the temperature meas urement are 100a and 20a. i 2 equal 100a. the variable k is boltzmann constant equal to 1.3806503*10 -23 m 2 kg/s 2 . the variable q is the electron charge constant equal to = 1.6*10 -19 c. the variable n is the ideality factor of the temperature diode. a typical value is near 1. the external temperature feature is a function of the auxiliary v shunt conversion time as well as converter averaging. the settings for the aforementioned registers directly impacts the accuracy of the measurement and the timing. entering\exiting the external temperature mode writing a 1 to d[0] of register 0xe2 will not configure the aux inputs to external temperature sense mode. the following series of commands need to be sent to enable external temperature sense functionality. 1. power-down the adc -- set bitd[6] of register 0xd2 to 1. 2. enable the ext temp bit -- set bitd[0] of register 0xde2 to 1. 3. power adc + and set measurement mode to temperature-- set bitd[6] to 0 and set bits[d 2:0] to 6 for register 0xd2. the external temperature feature is functional in both trigger and continuous modes. undoing the series of commands listed above will exit the external temperature mode. measurement registers 0xd6 read v shunt out (r) the read v shunt out register is a readable word register that stores the signed measured digital value of the primary v shunt input of the dpm. using equation 2 to calculate the integer value of the register, equation 8 calculates the floating point measured value for the primary v shunt channel. vshunt lsb is the numerical weight of each level for the v shunt channel, which equals 2.5v. 0x8b read v out (r) the read v out register is a readable word register that stores the unsigned measured digital value of the primary v bus input of the dpm. using equation 1 to calculate the integer value of the register, equation 9 calculates the floating point measured value for the primary v bus channel. vbus lsb is the numerical weight of each level for the v bus channel. the vbus lsb equals 1mv for the 60v version of the dpm and 250v for the 12v version of the dpm. 0x8c read i out (r) the read i out register is a readable word register that stores the signed measured digital value of the current passing through the primary channel?s shunt. the register uses the measured value from v shunt and the iout_cal_gain register. equation 10 yields the current for the primary channel. the register value is calculated using equation 2 on page 31 . the current lsb is calculated using equation 4 on page 33 . 0xd8 read peak min i out (r) 0xd9 read peak max i out (r) the read peak min/max i out registers are readable word registers that store the minimum and maximum current value of an averaging cycle for the current passing through the primary shunt. the min/max current tracking is enabled by setting the peak detect enable bit in the config_peak_det (0xd7) register. the current peak detect feature only works for the current register. at the conclusion of each primar y channel current, the dpm will record and store the minimum and maximum values of the current measured. the feature operates for both the trigger and continuous modes. disabling the peak detector enable bit will turn off the feature as well as clear the read peak min/max i out registers. 0x96 read p out (r) the read p out register is a signed readable word register that reports the digital value of the power from the primary channel. the register uses the values from read_iout and read_vshunt_out registers to calculate the power. the units for the power register are in watts. the power can be calculated using equation 11 . the register value is calculated using equation 2 . the power lsb can be calculated from equation 12 . the v buslsb equals 1mv for the 60v version of the dpm and 250v for the 12v version of the dpm. the current lsb is the value yielded from equation 4 on page 33. (eq. 8) vshunt register value vshunt lsb ? vbus register value vbus lsb ? figure 99. the isl28023 trac ks minimum and maximum average current readings (eq. 10) current register value current lsb ? (eq. 11) power register value power lsb ? 40000 ? power lsb current lsb vbus lsb ? (eq. 12) isl28023 36 fn8389.4 june 17, 2015 submit document feedback 0xe0 read v shunt out aux (r) the read v shunt out aux register is a readable word register that stores the signed measured digital value of the auxiliary v shunt input. use equation 2 to calculate the integer value of the register, equation 13 calculates the floating point measured value for the auxiliary v shunt channel. vshunt_aux lsb is the numerical weight of each level for the auxiliary v shunt channel. the vshunt_aux lsb equals 2.5v. 0xe1 read v out aux (r) the read v out aux register is a readable word register that stores the unsigned measured digital value of the auxiliary v bus input of the dpm. using equation 1 to calculate the integer value of the register, equation 14 calculates the floating point measured value for the auxiliary v bus channel. vbus lsb is the numerical weight of each level for the auxiliary v bus channel. the auxiliary vbus lsb equals 100v. the voltage range for the auxiliary v bus is 0 to v cc . 0x8d read temperature (r) the read temperature register is a readable word register that reports out the internal temperature of the chip. the register is a 16-bit signed register. bit15 of th e register is the signed bit. the register value can be calculated using equation 15 . n is the bit position within the re gister value. bit_val is the value of the bit either 1 or 0. the register value multiplied by 0.016 yields the internal temperature reading in centigrade (c). threshold detectors the dpm has three integrated comparators that allow for real time fault detection of overvoltag e, undervoltage for the primary v bus input and an overcurrent detection for the primary v shunt input. an over-temperature detection is available by multiplexing the input to the overvoltage comparator. 0xda v out ov threshold set (r/w) the v out ov threshold set register is a read writable word register that controls the th reshold voltage level to the overvoltage comparator. the desc ription of the functionality within this register is found in table 22 . the compared reference voltage le vel to the ov comparator is generated from a 6-bit dac. th e 6-bit dac has 4 or 6 voltage ranges to improve detection voltage resolution for a specific voltage range. ov_ot_sel d[9] the ov_ot_sel bit configures the multiplexer to the input of the ov comparator to either compare for over-temperature or overvoltage. setting the ov_ot_sel to a 1 configures the ov comparator to detect for an over-temperature condition. vbus_thres_rng d[8:6] the vbus_thres_rng bits sets the threshold voltage range for the overvoltage and undervoltage dacs. there are 6 selectable ranges for the 60v version of the dpm. only 4 selectable ranges for the 12v version of the dpm. table 23 defines the range settings for the v bus threshold detector. the yellow shaded row denotes the default setting. (eq. 13) vshunt_aux register value vshunt_aux lsb ? vbus register value vbus lsb ? register value 0 14 n bit_val n 2 n ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bit_val 15 2 15 ? ? ? ? ? ? figure 100. simplified block diagram of the threshold functions within the dpm table 22. 0xda v out ov threshold set register definition bit number d[15:10] d[9] d[8:6] d[5:0] bit name n/a ov_ot sel vbus_thres_ryng vbus_ov_ot_set default value 0000 00 0 0 00 11 1111 isl28023 37 fn8389.4 june 17, 2015 submit document feedback the temperature threshold reference level has one range setting which equals +125c at full-scale. vbus_ov_ot_set d[5:0] the vbus_ov_ot_set bits controls the voltage/temperature level to the input of the ov comparator. the lsb of the dac is 1.56% of the full-scale range chosen using the vbus_thres_rng bits. for the temperature feature, the lsb for the temperature level is 5.71c. the mathematical range is -144c to +221.4c. the overvoltage range starts at 25% of the full-scale range chosen using the vbus_thres_rng bits and ends at 125% of the chosen full-scale range. the same range applies to the temperature measurements. table 24 defines an abbreviated breakdown to set the ov/ot comparator level. the shaded row is the default condition. 0xdb v out uv threshold set (r/w) the v out uv threshold set register is a read writable byte register that controls the th reshold voltage level to the undervoltage comparator. the description of the functionality within this register is found in table 25 . the compared reference voltage level to the uv comparator is generated from a 6-bit dac. the 6-bit dac has 4 to 6 voltage ranges that are determined by the vbus_thres_rng bits in the v out ov threshold set register. vbus_uv_set d[4:0] the vbus_uv_set bits control the undervoltage level to the input of the uv comparator. the lsb of the dac is 1.56% of the full-scale range chosen using the vbus_thres_rng bits. the undervoltage ranges from 0% to 100% of the full-scale range set by the vbus_thres_rng bits. table 26 defines an abbreviated breakdown to set the undervoltage comparator levels. the shaded row is the default condition. 0xdc i out oc threshold set (r/w) the i out oc threshold set register is a read/writable word register that controls the th reshold current level to the overcurrent comparator. the description of the functionality within this register is found in table 27 . the overcurrent threshold is defined through the v shunt reading. the product of the current throug h the shunt resistor defines the v shunt voltage to the dpm. the current through the shunt resistor is directly proportional the v shunt voltage measured by the dpm. an overvoltage threshold for v shunt is the same as an overcurrent threshold. iout_ dir d[9] the iout_dir bit controls the polarity of the v shunt voltage threshold. the bit functionality a llows an overcurrent threshold to be set for currents flowing from vinp to vinm and the reverse direction. table 28 defines the range settings for the v bus threshold detector. the yellow shaded row denotes the default setting. table 23. vbus_thres_rng bits defined vbus_thres_rng: d[8:6] vbus_12v (range) vbus_60v (range) 0 0 0 12 48 00 1 624 01 0 312 01 11.255 1 0 0 x 3.3 1 0 1 x 2.5 table 24. vbus_ov_ot_set bits defined vbus_ov_ot_set: d[5:0] ov threshold value ot threshold value 00 0000 25% of fs -144 00 0001 (25 + 1.56)% of fs -138.3 00 0010 (25 + 3.12)% of fs -132.6 ............... .................... .................... 11 1101 (125 to 4.68)% of fs 210 11 1110 (125 to 3.12)% of fs 215.7 11 1111 (125 to 1.56)% of fs 221.4 table 25. 0xdb v out uv threshold set register definition bit number d[7:6] d[5:0] bit name n/a vbus_uv_set default value 00 00 0000 table 26. vbus_uv_set bits defined vbus_uv_set: d[5:0] uv threshold value 00 0000 0% 00 0001 1.56% of fs 00 0010 3.12% of fs ............... .................... 11 1101 (100 - 4.68)% of fs 11 1110 (100 - 3.12)% of fs 11 1111 (100 - 1.56)% of fs table 27. 0xdc i out oc threshold set register definition bit number d[15:10] d[9] d[8:7] d[6] d[5:0] bit name n/a iout_dir n/a v shunt thres rng vshunt_oc_set default value 0000 00 0 0 0 0 11 1111 table 28. vbus_thres_rng bits defined iout_dir: d[9] current direction 0 vinp to vinm 1vinm to vinp isl28023 38 fn8389.4 june 17, 2015 submit document feedback vshunt_thres_rng d[6] the vshunt_thres_rng bit sets the overvoltage threshold range for the overcurrent dac. the selectable v shunt range improves the overvoltage threshold resolution for lower full-scale current applications. table 29 defines the range settings for the v bus threshold detector. the yellow shaded row denotes the default setting. vshunt_oc_set d[5:0] the vshunt_oc_set bits control the v shunt voltage level to the input of the oc comparator. the lsb of the dac is 1.56% of the full-scale range chosen using the vshunt_thres_rng bits. the overvoltage range starts at 25% of the full-scale range chosen using vbus_thres_rng bits and ends at 125% of the chosen full-scale range. smb alert the dpm has two alert pins (smbalert1, smbalert2) to alert the peripheral circuitry that a fail ed event has occurred. smbalert1 output is an open drain allowing the user the flexibility to connect the alert pin to other componen ts requiring different logic voltage levels than the dpm. the smbalert2 has a push/pull output stage for driving pins with logic voltage levels equal to the voltage applied to i2cvcc pin. the push/pull output is useful for driving peripheral components that require the dpm to source and sink a current. the alert pins are commonly connected to an interrupt pin of a microcontroller or an enable pin of a device. the smb alert registers control the functionality of the smb alert pins. the threshold comparators are the inputs to the smb alert registers. the outputs are the smb alert pins. figure 101 is a simple functional bl ock diagram of the smb alert features. table 29. vshunt_thres_rng bit defined vshunt_thres_rng: d[6] v shunt (range) 0 80mv 1 40mv table 30. vshunt_oc_set bits defined vshunt_oc_set: d[5:0] oc threshold value 00 0000 25% of fs 00 0001 (25 + 1.56)% of fs 00 0010 (25 + 3.12)% of fs ............... .................... 11 1101 (125 - 4.68)% of fs 11 1110 (125 - 3.12)% of fs 11 1111 (125 - 1.56)% of fs figure 101. simplified block diagram of the smb alert functions within the dpm isl28023 39 fn8389.4 june 17, 2015 submit document feedback 0xdd configure interrupts (r/w) the configure interrupt register is a read/writable word register that controls the behavior of the two smb alert pins. the definition of the control bits within the configure interrupt register is defined in table 31 . alert2_feedthr d[14:12] the alert2_feedthr bits determine whether the bit from each alert comparator is digitally conditioned or not. the alert comparators, digital filters and latching bits are the same for both smb alert channels. table 32 defines the functionality of the alert2_feedthr bits. alert1_feedthr d[11:9] the alert1_feedthr bits determine whether the bit from each alert comparator is digitally conditioned or not. the alert comparators, digital filters and latching bits are the same for both smb alert channels. table 33 defines the functionality of the alert1_feedthr bits. oc_fil d[8:7] the oc_fil bits control the digital filter for the overcurrent circuitry. the digital filter will prevent short duration events from passing to the output pins. the filt er is useful in preventing high frequency power glitches from triggering a shutdown event. the filter time delay ranges from 0s to 8s. an 8s filter setting requires an error event to be at least 8s in duration before passing the result to the smb aler t pins. there is one oc digital filter for both smb alert pins. configuring oc_fil bits will change the oc digital filter setting for both smb alert pins. see table 34 for the filter selections. uv_fil d[6:5] the uv_fil bits control the digi tal filter for the undervoltage circuitry. the digital filter will pr event short duration events from passing to the output pins. the filter is useful in preventing high frequency power glitches from triggering a shutdown event. the filter time delay ranges from 0s to 8s. an 8s filter setting requires an error event to be at least 8s in duration before passing the result to the smb alert pins. there is one uv digital filter for both smb alert pins. configuring uv_fil bits will change the uv digital filter setting for both smb alert pins. see table 34 for the filter selections. ov_fil d[4:3] the ov_fil bits control the digital filter for the overvoltage circuitry. the digital filter will pr event short duration events from passing to the output pins. the filter is useful in preventing high frequency power glitches from triggering a shutdown event. the filter time delay ranges from 0s to 8s. an 8s filter setting requires an error event to be at least 8s in duration before passing the result to the smb alert pins. there is one ov digital filter for both smb alert pins. conf iguring ov_fil bits will change the ov digital filter setting for both smb alert pins. see table 34 for the filter selections. oc_en d[2] the oc_en enable bit controls the power to the overcurrent dac and comparator. setting the bit to 1 enables the overcurrent circuitry. ov_en d[1] the ov_en enable bit controls the power to the overvoltage dac and comparator. setting the bit to 1 enables the overvoltage circuitry. uv_en d[0] the uv_en enable bit controls the power to the undervoltage dac and comparator. setting the bit to 1 enables the undervoltage circuitry. table 31. 0xdd configure interrupt register definition bit number d [15] d [14:12] d [11:9] d [8:7] d [6:5] d [4:3] d [2] d [1] d [0] bit name n/a alert2 feedth alert1 feedth oc fil ov fil uv fil oc en ov en uv en default value 0 000 000 0 0 00 0 0 0 0 0 table 32. alert2_feedthr bits defined alert2_feedthr bits d[14:12] bit val functionality d[14] 0 0 ov/ot digitally conditioned 1ov/ot pass through d[13] 1 0 uv digitally conditioned 1uv pass through d[13] 2 0 oc digitally conditioned 1oc pass through table 33. alert1_feedthr bits defined alert1_feedthr bits d[11:9] bit val functionality d[11] 0 0 ov/ot digitally conditioned 1ov/ot pass through d[10] 1 0 uv digitally conditioned 1uv pass through d[9] 2 0 oc digitally conditioned 1 oc pass through table 34. digital glitch filter settings defined oc_fil d[8:7] uv_fil d[6:5] ov_fil d[4:3] filter time (s) 0 0 0 01 2 10 4 11 8 isl28023 40 fn8389.4 june 17, 2015 submit document feedback 0xde force feedthrough alert register (r/w) the force feedthrough alert register is a read/writable byte register that controls the polarity of the interrupt. the definition of the control bits within the force feedthrough alert register is defined in table 35 . a2pol d[3], a2pol d[2] the axpol bits control the polari ty of an interrupt. a2pol bit defines the smbalert2 pin active interrupt state. a1pol bit defines the smbalert1 pin active interrupt state. table 36 defines the functionality of the bit. forcea2 d[1], forcea1 d[0] the forceax bits allow the user to force an interrupt by setting the bit. forcea2 bit controls the smbalert2 pin state. forcea1 bit controls the smbalert1 pin state. table 37 defines the functionality of the bit. 0x03 clear faults (s) the clear faults register is a se nd byte command that clears all faults pertaining to the status registers. upon execution of the command, the status registers return to the default state defined in table 2 . 0x7a status v out (r/w) the status v out register is a read/writable byte register that reports over and undervoltage warnings for the v bus input. v out ov warning d[6] the v out ov warning bit is set to 1 when an overvoltage fault occurs on the v bus input. the v bus overvoltage threshold is set from the v out ov threshold set register. in the event of a v bus overvoltage condition, the v out ov warning is latched to 1. writing a 1 to the v out ov warning bit will clear the warning resulting in a bit value equal to 0. v out uv warning d[5] the v out uv warning bit is set to 1 when an undervoltage fault occurs on the v bus input. the v bus undervoltage threshold is set from the v out uv threshold set register. in the event of a v bus undervoltage condition, the v out uv warning is latched to 1. writing a 1 to the v out uv warning bit will clear the warning resulting in a bit value equal to 0. 0x7b status i out (r/w) the status i out register is a read/writable byte register that reports an overcurrent warning for the v shunt input. i out oc warning d[5] the i out oc warning bit is set to 1 when an overcurrent fault occurs on the v shunt input. the v shunt overcurrent threshold is set from the i out oc threshold set register. in the event of a v shunt overcurrent condition, the i out oc warning is latched to 1. writing a 1 to the i out oc warning bit will clear the warning resulting in a bit value equal to 0. 0x7d status temperature (r/w) the status temperature register is a read/writable byte register that reports an over-temperatu re warning initiated from the internal temperature sensor. ot warning d[6] the ot warning bit is set to 1 when an over-temperature fault occurs from the internal temperature sensor. the over-temperature threshold is set from the v out ov threshold set register. in the event of an over-temperature condition, the ot warning bit is latched to 1. writing a 1 to the ot warning bit will clear the warning resulting in a bit value equal to 0. table 35. 0xde force feedthrough alert register definition bit number d[7:4] d[3] d[2] d[1] d[0] bit name n/a a2pol a1pol force a2 force a1 default value 0000 0 0 0 0 table 36. axpol bit defined a2pol d[3], a1pol d[2] interrupt active state 0 low 1high table 37. forceax bit defined forcea2 d[1], forcea1 d[0] interrupt status 0 normal 1 interrupt forced table 38. 0x7a status v out register definition bit number d[7] d[6] d[5] d[4:0] bit name n/a v out ov warning v out uv warning n/a default value 0 0 0 0 0000 table 39. 0x7b status i out register definition bit number d[7] d[6] d[5] d[4:0] bit name n/a n/a i out oc warning n/a default value 0 0 0 0 0000 table 40. 0x7d status temperature register definition bit number d[7] d[6] d[5] d[4:0] bit name n/a ot warning n/a n/a default value 0 0 0 0 0000 isl28023 41 fn8389.4 june 17, 2015 submit document feedback 0x7e status cml (r/w) the status cml register is a read/writable byte register that reports warnings and errors a ssociated with communications, logic and memory. uscmd d[7] the uscmd bit is set to 1 when an unsupported command is received from the i 2 c master. reading from an undefined register is an example of an acti on that would set the uscmd bit. the uscmd bit is a latched bit. writing a 1 to the uscmd bit clears the warning resulting in a bit value equal to 0. usdata d[6] the usdata bit is set to 1 when an unsupported data is received from the i 2 c master. writing a word to a byte register is an example of an action that would set the usdata bit. the usdata bit is a latched bit. writing a 1 to the usdata bit clears the warning resulting in a bit value equal to 0. pecerr d[5] the pecerr bit is set to 1 when a packet error check (pec) event has occurred. writing the wrong pec to the dpm is an example of an action that would set the pecerr bit. the pecerr bit is a latched bit. writing a 1 to the pecerr bit clears the warning resulting in a bit value equal to 0. comerr d[1] the comerr bit is set to 1 for communication errors that are not handled by the uscmd, usdata and pecerr errors. reading from a write only register is an example of an action that would set the comerr bit. the comerr bit is a latched bit. writing a 1 to the comerr bit clears the warning resulting in a bit value equal to 0. 0x78 status byte (r/w) the status byte register is a read /writable byte register that is a hierarchal register to the stat us temperature and status cml registers. the status byte regi sters bits are set if an over temperature or a cml error has occurred . busy d[7] the busy bit is set to 1 when the dpm is busy and unable to respond. the busy bit is a latched bit. writing a 1 to the busy bit clears the warning resulting in a bit value equal to 0. temperature d[2] the temperature bit is set to 1 when an over-temperature fault occurs from the internal temperature sensor. this bit is the same action bit as the ot warning bit in the status temperature register. the over-temperature threshold is set from the v out ov threshold set register. in the event of an over-temperature condition, the temperature bit is latched to 1. writing a 1 to the temperature bit will clear the warning resulting in a bit value equal to 0. cml d[1] the cml bit is set to 1 when any errors occur within the status cml register. there are four status cml error bits that can set the cml bit. the cml bit is a latc hed bit. writing a 1 to the cml bit clears the warning resulting in a bit value equal to 0. 0x79 status word (r/w) the status word register is a read writable word register that is a hierarchal register to the status v out , status i out and status byte registers. the status word registers bits are set when any errors previously described occur. the register generically reports all errors. v out d[15] the v out bit is set to 1 when any errors occur within the status v out register. whether either or both an undervoltage or overvoltage fault occurs, the v out bit will be set. the v out bit is a latched bit. writing a 1 to the v out bit clears the warning resulting in a bit value equal to 0. i out d[14] the i out bit is set to 1 when an overcurrent fault occurs. this bit is the same action bit as the i out oc warning bit in the status i out register. in the event of an overcurrent condition, the i out bit is latched to 1. writing a 1 to the i out bit will clear the warning resulting in a bit value equal to 0. 0x1b smbalert mask (br/bw) 0xdf smbalert2 mask (br/bw) the smbalert registers are bloc k read/writable registers that mask error conditions from electrically triggering the respective smbalert pin. the smbalert can mask bits of any of the status registers. masking lower level bits prevents hierarchal bit from being set. for example, a comerr bit being masked will not set the cml bit of the status byte register. to mask a bit, the first data byte is the register address of the bit(s) to be masked. the second and third data bytes are the masking bits of the register. a masking bit of 1 prevents the signal from triggering an interrupt. table 41. 0x7e status cml register definition bit number d[7] d[6] d[5] d[4:2] d[1] d[0] bit name uscmd usdata pecerr n/a comerr n/a default value 0 0 0 0 00 0 0 table 42. 0x78 status byte register definition bit number d[7] d[6:3] d[2] d[1] d[0] bit name busy n/a temperature cml n/a default value 0 000 0 0 0 0 table 43. 0x79 status word register definition bit number d[15] d[14] d[13:8] d[7:0] bit name v out i out n/a see status byte default value 0 0 00 0000 0000 0000 isl28023 42 fn8389.4 june 17, 2015 submit document feedback all alert bits are masked as the default state for both the smb alert pins. the master needs to se nd instructions to unmask the alert bits. as an example, a user would like to allow the comerr bit to trigger a smbalert2 interrupt while masking the rest of the alerts within the status cml regi ster. the command that is sent from the master to the dpm is the slave address, smbalert2 register address, status cml re gister address and the mask bit value. in a hexadecimal format, the data sent to the dpm is as follows; 0x80 df 7e fd. to read the mask status of any alert register, a four byte write command, without pec, consisting of the slave address of the device, the smb mask register a ddress, the number of bytes to be read back and the register address of the mask to be read. once the write command has commenced, a read command consisting of the device slave ad dress and the register address of the smb mask will return the mask of the desired alert register. as an example, a user would like to read the status of the status byte register. the first command sent to the dpm is in hexadecimal bytes is 0x82 1b 01 78. the second command is a standard read. the slave address is 0x83 (0x82 + read bit set) and the register address is 0x1b. smbalert1 response address it is common that the smbale rt1 pin of each isl28023 device is shared to a single gpio pin of the microcontroller. the smbalert1 pin is an open drain allowing for multiple devices to be or?ed to a single gpio pin. the smbalert1 response addre ss command reports the slave address of the device that has triggered alert. the smb respond address command is shown in figure 102 . the alert response address is 0x18. in the event of multiple alerts pulling down the gpio line, the alert respond command will return the lowest slave addr ess that is connected to the i 2 c bus. upon clearing the lowest slave address alert, the alert command will return the lowest slave address of the remaining alerts that are activated. the alert response is operable when the interrupt active state is forced low by the device at the smbalert1 pin. changing smbalert1 interrupt polarity or forcing an interrupt will enable the alert response. by design, th e open drain of the smbalert1 pin allows for anding of the inte rrupt via a pull-up resistor. the alert response command is vali d for only the smbalert1 pin. the alert response command will return a 0x19 when there are no errors that are detected. external clock control the dpm has an external clock feature that allows the chip to be synchronized to an external clock. the feature is useful in limiting the number of clocks running as ynchronously within a system. 0xe5 configure external clock (r/w) the configure external clock regi ster is a read writable byte register that controls the functionality of the external clock feature. extclk_en d[7] the extclk_en bit enables the external clock feature. the extclk_en default bit setting is 0 or disabled. a bit setting of 1 disables the internal oscillator of the dpm and connects circuitry such that the system clock is ro uted from the external clock pin. smbalert2_oen d[6] the smbalert2_oen bit within the configure external clock register either enables or disables the buffer that drives the smbalert2 pin. extclkdiv d[3:0] the extclkdiv bits control an intern al clock divider that is useful for fast system clocks. the intern al clock frequency from pin to chip is represented in equation 16 . f extclk is the frequency of the signal driven to the external clock pin. clkdiv is the decimal value of the clock divide bits. voltage margin the voltage margining feature within the dpm is commonly used as a means of testing the robustness of a system. the voltage dac from the dpm is connected to a summation circuit allowing the voltage sourced from the dac to raise or lower the overall voltage supply to system. a si mplified block diagram is illustrated in figure 103 . figure 102. the command structure of the smbalert response address table 44. 0xe5 configure external clock register definition bit number d[7] d[6] d[5:4} d[3:0] bit name extclk_en smblalert2 oen n/a extclkdiv default value 0 0 00 0000 table 45. smbalert2_oen bit defined smbalert_oen smbalert2 status 0 disabled 1enabled (eq. 16) freq internal f extclk clkdiv 8 ? ()8 ? isl28023 43 fn8389.4 june 17, 2015 submit document feedback the voltage margining feature can be used to improve accuracy of the voltage applied to the lo ad of a system. for nonfeedback driving applications, the sense resistor used to measure current to the load reduces the voltage to the load. the voltage drop from the sense resistor can be a large percentage with respect to the supply voltage for point of load applications. 0xe4 configure vol margin (r/w) the configure vol margin register is a read/writable byte register that controls the functionality of the voltage margin dac. mdac_hs d[5:3] the mdac_hs bits control the half -scale output voltage from the margin dac. there are 8 half-sca le voltages the margin dac can be programmed to. table 47 lists the selections. the voltage at the dac_out is the value of the mdac_hs setting when the set vol margin register equals 0x80. load d[2] the load bit programs the set vol margin register to the dac. the dac is programmed when the load bit is programmed from a 0 to a 1. dac_oen d[1] the dac_oen bit either enables or disables the output of the margin dac. setting the bit to a 1 connects the output of the margin dac to the dac_out pin. dac_en d[0] the dac_en bit either enables or disables the margin dac circuitry. setting the bit to a 1 powers up the margin dac making it operational to use. 0xe3 set vol margin (r/w) the set vol margin register is an unsigned read/writable byte register that controls the output voltage of the margin dac referenced to the half-scale setting. the full-scale voltage is twice the half-scale range minus the dac lsb for the margin dac half-scale range. a half-scale setting of 1.0v has a full-scale setting of 1.992v. the lsb for the margin dac is a function of the half-scale setting. using equation 17 , the lsb for the margin dac is calculated as; mdac hs is the half-scale setting for the voltage dac. the vol margin register value for programming the dac to a specific voltage is calculated using equation 18 . the value for vout desired ranges from 0v to two times the mdac hs value minus one mdac lsb . figure 103. simplified block diagram of the margin dac functions within the dpm table 46. 0xe4 configure vol margin register definition bit number d[7:6] d[5:3] d[2] d[1] d[0] bit name n/a mdac_hs load dac_oen dac_en default value 00 00 0 0 0 0 table 47. mdac_hs bits defined mdac_hs[2:0] half-scale voltage (v) 0 0 0 0.4 001 0.5 010 0.6 011 0.7 100 0.8 101 0.9 110 1.0 111 1.2 table 48. 0xe3 set vol margin register definition bit number d[7:0] bit name mdac[7:0] default value 0000 0000 (eq. 17) mdac lsb 2 mdac hs ? ? ? 2 8 2 mdac hs ? 256 mdac value integer vout desired mdac lsb ? ? ? ? ? ? (eq. 18) isl28023 44 fn8389.4 june 17, 2015 submit document feedback smbus/i 2 c serial interface the isl28023 supports a bidirectio nal bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving devi ce as the receiver. the device controlling the transfer is th e master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and receive operations. therefore, the isl28023 operates as a slave device in all applications. the isl28023 uses two bytes data transfer, all reads and writes are required to use two data by tes. all communication over the i 2 c interface is conducted by sendin g the msbyte of each byte of data first, followed by the lsbyte. protocol conventions for normal operation, data stat es on the sda line can change only during scl low periods. sda state changes during scl high are reserved for indicating start and stop conditions (see figure 104 ). on power-up, the sda pin is in the input mode. all i 2 c interface operations must begin with a start condition, which is a high-to-low transition of sda while scl is high. the device continuously monitors th e sda and scl lines for the start condition and does not respon d to any command until this condition is met (see figure 104 ). a start condition is ignored during the power-up sequence. all i 2 c interface operations must be terminated by a stop condition, which is a low-to-high transition of sda while scl is high (see figure 104 ). a stop condition at the end of a read operation or at the end of a write operation places the device in its standby mode. smbus, pmbus support the isl28023 supports smbus and pmbus protocol, which is a subset of the global i 2 c protocol. smbclk and smbdat have the same pin functionality as the sc l and sda pins, respectively. the smbus operates at 100khz. the pmbus protocol standardizes the functionality of each register by address. figure 104. valid data change s, start and stop conditions figure 105. acknowledge response from receiver figure 106. byte write sequence (s lave address indicated by nnnnnn) sda scl start data data stop stable change data stable sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high high impedance s t a r t identification byte data byte a c k signals from the master signals from the isl28023 a c k 10 n nn write signal at sda 0000 nnn address byte s t o p data byte a c k a c k isl28023 45 fn8389.4 june 17, 2015 submit document feedback device addressing following a start condition, th e master must output a slave address byte. the 7 msbs are the device identifiers. the a0, a1 and a2 pins control the bus addr ess (these bits are shown in table 49 ). there are 55 possible co mbinations depending on the a0, a1 and a2 connections. the last bit of the slave addre ss byte defines a read or write operation to be performed. when this r/w bit is a ?1?, a read operation is selected. a ?0? selects a write operation (refer to figure 102 ). after loading the entire slave address byte from the sda bus, the device compares with the internal slave address. upon a correct compare, the device outputs an acknowledge on the sda line. table 49. i 2 c slave addresses a2 a1 a0 slave address gnd gnd gnd 1000 000 gnd gnd i2cvcc 1000 001 gnd gnd sda 1000 010 gnd gnd scl 1000 011 gnd i2cvcc gnd 1000 100 gnd i2cvcc i2cvcc 1000 101 gnd i2cvcc sda 1000 110 gnd i2cvcc scl 1000 111 gnd sda gnd 1001 000 gnd sda i2cvcc 1001 001 gnd sda sda 1001 010 gnd sda scl 1001 011 gnd scl gnd 1001 100 gnd scl i2cvcc 1001 101 gnd scl sda 1001 110 gnd scl scl 1001 111 i2cvcc gnd gnd 1010 000 ............... .............. .............. .................. i2cvcc scl scl 1011 111 sda gnd gnd 1100 000 sda gnd vcc do not use. reserved ............... .............. .............. .................. sda scl scl 1101 111 scl gnd gnd 1110 000 ............... .............. .............. .................. scl sda x do not use. reserved scl scl x do not use. reserved isl28023 46 fn8389.4 june 17, 2015 submit document feedback following the slave byte is a one byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power-up, the internal address counter is set to address 00h, so a current address read starts at address 00h. when required, as part of a random read, the master must supply the one word address bytes, as shown in figure 108 . in a random read oper ation, the slave byte in the ?dummy write? portion must match the slave byte in the ?read? section. for a random read of the registers, the slave byte must be ?1nnnnnnx? in both places. write operation a write operation requires a start condition, followed by a valid identification byte, a valid address byte, two data bytes and a stop condition. the first data byte contains the msb of the data, the second contains the lsb. after each of the four bytes, the device responds with an ack. at this time, the i 2 c interface enters a standby state. read operation a read operation consists of a three byte instruction, followed by two data bytes (see figure 108 ). the master initiates the operation issuing the following sequence: a start, the identification byte with the r/w bit set to ?0?, an address byte, a second start and a second identification byte with the r/w bit set to ?1?. after each of the three bytes, the isl28023 resp onds with an ack. then the isl28023 transmits two data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of the first byte. the master termin ates the read operation (issuing no ack then a stop condition) follo wing the last bit of the second data byte (see figure 108 ). the data bytes are from the memory location indicated by an internal pointer. this pointer?s in itial value is determined by the address byte in the read operatio n instruction and increments by one during transmission of each pair of data bytes. group command the dpm has a feature that allows the master to configure the settings of all dpm chips at once . the configuration command for each device does not have to be same. device 1 on an i 2 c bus could be configured to set the voltage threshold of the ov comparator while device 2 is configured for the acquisition time of the v bus input. to achieve the scenario described without group command, the master sends two write commands, one to each slave device. each command sent from the master has a start bit and a stop bit. the group command protocol concatenates the two commands but replaces the stop bit of the first command and the start bit of the second command with a repeat start bit. the actions sent in a group command format will execute once the stop bit has been sent. the stop bit signifies the end of a packet. the broadcast feature saves time in configuring the dpm as well as measuring signal parameters in time synchronization. the broadcast should not be used for dpm read backs. this will cause all devices connected to the i 2 c bus to talk to the master simultaneously. figure 107. slave address, word address and data bytes d15 d14 d13 d10 d12 d11 d9 d8 a0 a7 a2 a4 a3 a1 data byte 1 a6 a5 1 nn n n n r/w n word address d7 d6 d5 d2 d4 d3 d1 d0 slave address byte data byte 2 signals from the master signals from the slave signal at sda s t a r t identification byte with address byte a c k a c k 0 s t o p 1 identification byte with a c k s t a r t second read data byte first read data byte a c k 1n n nnnn 1n n nn nn r/w = 0 r/ w = 1 isl28023 47 fn8389.4 june 17, 2015 submit document feedback clock speed the device supports high-speed digital transactions up to 3.4mbs. to access the high speed i 2 c feature, a master byte code of 0000 1xxx is attached to the beginning of a standard frequency read/write i 2 c protocol. the x in the master byte signifies a ?do not care state?. x can either equal a 0 or a 1. the master byte code should be clocked into the chip at frequencies equal or less than 400khz. the master code command configures the internal filters of the isl28023 to permit data bit frequencies greater than 400khz . once the master code has been clocked into the device, the protocol for a standard read/ write transaction is followed. the frequency at which the standard protocol is clocked in at can be as great as 3.4mhz. a stop bit at the end of a standard protocol will terminate the high speed transaction mode. appending another standard protocol serial transaction to the data st ring without a stop bit, will resume the high speed di gital transaction mode. figure 109 illustrates the data sequence for the high speed mode. the minimum i 2 c supply voltage when oper ating at clock speeds of 400khz is 1.8v. signal integrity the purity of the signal being measured by the isl28023 is not always ideal. environmental noise or noise generated from a regulator can degrade the measurement accuracy. the isl28023 maintains a high cmrr ratio from dc to approximately 10khz, as shown in figure 110 . the cmrr vs frequency graph best represents the response of the isl28023 when an aberrant sign al is applied to the circuit. the graph was generated by shorting the isl28023 v shunt inputs without any filtering and applying a 0 to 20v sine wave to the shunt inputs, vinp and vinm. a 0 to 3v sine wave was applied to the auxiliary v shunt inputs, auxp and auxm. the voltage range from a 1024 sample set was recorded for each frequency applied to shunt input. cmrr resu lts prior to 10khz are mostly a result of the variability of the measurement due to the programmed acquisition time. the input is not able to bleed through the noise floor. the cmrr can be improved by desi gning a filter stage before the isl28023. the purpose of the filter stage is to attenuate the amplitude of the unwanted signal to the noise level of the isl28023. figure 111 is a simple filter example to attenuate unwanted signals. measuring large currents requires low value sense resistors. a large valued capacitor is required to filter low frequencies if the shunt capacitor, c sh is connected directly in parallel to the sense resistor, r sh . for more manageable capacitor values, it may be better to directly connect the shunt resistor across the shunt inputs of the isl28023. the conne ction is illustrated in figure 111 . a single pole filter constructed of 2 resistors, r 1 , and c sh will improve capacitor value selections for low frequency filtering. r 1 and c 1 at both shunt inputs are single ended low pass filters. the value of the series resistor to the isl28023 can be a larger value than the shunt resistor, r sh . a larger series resistor to the input allows for a lower cutoff frequency filter design to the isl28023. the isl28023 inputs can source up to 20a of transient current in the measur ement mode. the transient or switching offset current can be as large as 10a. the switching offset current combined with the series resistance, r 1 , creates an error offset voltage. a balance of the value of r 1 and the shunt measurement error should be achieved for this filter design. the common mode voltage of the shunt input stage ranges from 0v to 60v. the capacitor voltage rating for c 1 and c sh should comply with the nominal voltage being applied to the input. fast transients an small isolation resistor placed between isl28023 inputs and the source is recommended. in hot swap or other fast transient events, the amplitude of a signal can exceed the recommended operating voltage of the part du e to the line inductance. the isolation resistor creates a low pa ss filter between the device and the source. the value of the isolation resistor should not be too large. a large value isolation resistor can effect the measurement accuracy. the value of the isolation resistor combined with the offset current creates an offset voltage error at the shunt input. the input of the bus channel is connected to the top of a precision resistor divider. the accuracy of the resistor divider determines the gain erro r of the bus channel. the input resistance of the bus channel is 600k . placing an isolation resistor of 10 will change the gain error of the bus channel by 0.0016%. figure 110. cmrr vs frequency 90 95 100 105 110 115 120 125 130 10 100 1k 10k 100k frequency (hz) gain (db) time = 2.048ms time = 1.024ms time = 0.512ms time = 0.256ms time = 0.128ms time = 0.64ms load r sh from source isl28023 r 1 r 1 c sh c 1 c 1 isl28023 48 fn8389.4 june 17, 2015 submit document feedback external clock an externally controlled clock allows measurements to be synchronized to an event that is time dependent. the event could be application generated, such as timing a current measurement to a charging capacitor in a switch regulator application or the event could be environmental. a voltage or current measurement may be susceptible to crosstalk fr om a controlled source. instead of filtering the environmental noise from the measurement, another approach would be to synchronize the measurement to the source. the variability and a ccuracy of the measurement will improve. the isl28023 has the functionality to allow for synchronization to an external clock. the speed of the external clock combined with the choice of the internal chip frequency division value determines the acquisition times of the adc. the internal system clock frequency is 500khz. the inte rnal system clock is also the adc sampling clock. the acquisit ion times scale linearly from 500khz. for example, an external clock frequency of 4.0mhz with a frequency divide setting of 0 (internal divide by 8) results in acquisition times that equal the internal oscillator frequency when enabled. the adc modulator is optimized for frequencies of 500khz. operating internal clock frequencies beyond 500khz may result in measurement accuracy errors due to the modulator not having enough time to settle. suppose an external clock frequenc y of 5.5mhz is applied with a divide by 88 internal frequency se tting, the system clock speed is 62.5khz or 8x slower than the internal system clock. the acquisition times for this example will increase by 8. for a channel?s conversion time setti ng of 2.048ms, the isl28023 will have an acquisit ion time of 256s. figure 113 illustrates a simple math ematical diagram of the eclk pin internal connection. the external clock divide is controlled by way of the extclkdiv bit in register 0xe5. figure 114 illustrates how changing the system clock frequency effects the measurement bandwidth (the adc acquisition time). the bandwidth of the external clock circuitry is 25mhz. figure 115 shows the bandwidth of the external clock circuitry when the external clock division bits equals to 0. figure 112. simplified sc hematic of the isl28023 synchronized to a mcu system clock load vout = 0.6 + (0.6 ? dac out) * r2/r1 i 2 c smbus a1 scl sda vinp gnd adc 16-bit sw mux pmbus reg map a0 isl28023 vcc vinm vbus fb isl85415 en pg gnd vcc,fs,ss vin a2 8-bit dac dac out lo phase sync,comp 1uf to smbalert1 0.1f boot v in = 4.5v to 36v r 2 r 1 vmcu gnd gpio/int sda gpio scl r_pullup r_pullup mcu smbalert2 i2cvcc 3.3v vreg vreg_in vreg_out v in rsh auxv auxp auxm ext_temp place diode near rsh temp sense v in smbalert1 ext clk gpio system_clock sync -15.5 -13.5 -11.5 -9.5 -7.5 -5.5 -3.5 -1.5 0.5 10 100 1k 10k 100k frequency (hz) gain (db) freqextclk = 16mhz adc time setting (config_ichannel) = 0 extclkdiv = 1 extclkdiv = 3 extclkdiv = 4 extclkdiv = 14 extclkdiv = 0 -8.5 -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 0.01 0.1 1 10 100 extclk frequency (mhz) gain (db) extdiv = 0; (freq int = freq extclk /8) isl28023 49 fn8389.4 june 17, 2015 submit document feedback the external clock pin can acce pt signal frequencies above 25mhz by programming the system clock frequency such that the internal clock frequency is below 25mhz. figure 116 illustrates the effects of dividing the external clock frequency on the v shunt measurement accuracy. figures 115 and 116 were generated by applying a dc voltage to the v shunt input and measuring the signal by way of an adc conversion. overranging it is not recommended to operate the isl28023 outside the set voltage range. in the event of measuring a shunt voltage beyond the maximum set range (80mv) and lower than the clamp voltage of the protection diode (1v), the measured output reading may be within the accepted range but will be incorrect. shunt resistor selection in choosing a sense resistor, th e following resistor parameters need to be considered: the resistor value, resistor temperature coefficient and resistor power rating. the sense resistor value is a function of the full-scale voltage drop across the shunt resistor and the maximum current measured for the application. the maximum measurable range for the v shunt input (vinp-vinm) of the isl28023 is 80mv. the isl28023 allows the user to defi ne a unique range other than 80mv. once the voltage range for the input is chosen and the maximum measurable current is known, the sense resistor value is calculated using equation 19 . in choosing a sense resistor, th e sense resistor power rating should be taken into consideration. the physical size of a sense resistor is proportional to the power rating of the resistor. the maximum power rating for the measurement system is calculated as the v shunt_range multiplied by the maximum measurable current expected. the power rating equation is represented in equation 20 . a general rule of thumb is to multiply the power rating calculated in equation 20 by 2. this allows the sense resistor to survive an event when the current passing through the shunt resistor is greater than the measurable maximum current. the higher the ratio between the power rating of the chosen sense resistor and the calculated power rating of the system ( equation 20 ), the less the resistor will heat up in high current applications. the temperature coefficient (tc) of the sense resistor directly degrades the current measurement accuracy. the surrounding temperature of the sense resistor and the power dissipated by the resistor will cause the sense resistor value to change. the change in resistor temperature with respect to the amount of current that flows through the resist or is directly proportional to the ratio of the power rating of the resistor versus the power being dissipated. a change in se nse resistor temperature results in a change in sense resistor value. overall, the change in sense resistor value contributes to the measurement accuracy for the system. the change in a resistor value due to a temperature rise can be calculated using equation 21 . ? temperature is the change in temperature in celsius. rsense tc is the temperature coefficient rating for a sense resistor. r sense is the resistance value of the sense resistor at the initial temperature. table 50 is a shunt resistor look up table for select full-scale current measurement ranges (imeas max ). table 50 also provides the minimum rating for each shunt resistor. figure 116. external clock vs external bit value -8.5 -7.5 -6.5 -5.5 -4.5 -3.5 -2.5 -1.5 -0.5 0.5 012345678910111213141516 extclkdiv bit value gain (db) extclk frequency = 45mhz (eq. 19) r sense v shunt_range imeas max table 50. shunt resistor values and power ratings for select measurable current ranges r sense /p rating vshunt range (pga setting) imeas max 80mv 100a 800 /8w 1ma 80 /80w 10ma 8 /800w 100ma 800m /8mw 500ma 160m /40mw 1a 80m /80mw 5a 16m /400mw 10a 8m /800mw 50a 1.6m /4w 100a 0.8m /8w 500a 0.16m /40w (eq. 20) p res_rating v shunt_range imeas max ? ? r sense r sense rsense tc ?? temperature ? isl28023 50 fn8389.4 june 17, 2015 submit document feedback it is often hard to readily purc hase shunt resistor values for a desired measurable current range. either the value of the shunt resistor does not exist or the power rating of the shunt resistor is too low. a means of circumventing the problem is to use two or more shunt resistors in parall el to set the desired current measurement range. for example, an application requires a full-scale current of 100a with a maximum voltage drop across the shunt resistor of 80mv. from table 50 , this requires a sense resistor of 0.8m , 8w resistor. assume the power ratings and the shunt resistor values to chose from are 1m ? 4w, 2m /4w and 4m /4w. let?s use a 1m and a 4m resistor in parallel to create the shunt resistor value of 0.8m . figure 117 shows an illustration of the shunt resistors in parallel. the power to each shunt resistor should be calculated before calling a solution complete. the power to each shunt resistor is calculated using equation 22 . the power dissipated by the 1m resistor is 6.4w. 1.6w is dissipated by the 4m resistor. 1.6w exceed s the rating limit of 1w for the 1m sense resistor. another approach would be to use three shunt resistors in parallel as illustrated in figure 118 . using equation 22 , the power dissipated to each shunt resistor yields 3.2w for the 2m shunt resistors and 1.6w for the 4m shunt resistor. all shunt resistors are within the specified power ratings. lossless current sensing (dcr) a dcr sense circuit is an alternat ive to a sense resistor. the dcr circuit utilizes the parasitic resist ance of an inductor to measure the current to the load. a dcr circuit remotely measures the current through an inductor. the lack of components in series with the regulator to the lo ad makes the circuit lossless. a properly matched dcr circuit has an equivalent circuit seen by the adc equals to r dcr in figure 119 . before deriving the transfer function between the inductor current and voltage seen by the isl28023, let?s review the definiti on of an inductor and capacitor in the laplacian domain. x c is the impedance of a capacitor related to the frequency and x l is the impedance of an inductor related to frequency. equals to 2 ? f. f is the chop frequency dict ated by the regulator. using ohms law, the voltage across the dcr circuit in terms of the current flowing through the inductor is defined in equation 24 . in equation 24 , r dcr is the parasitic resistance of the inductor. the voltage drop across the indu ctor (lo) and the resistor (r dcr ) circuit is the same as the voltage drop across the resistor (r sen ) and the capacitor (c sen ) circuit. equation 25 defines the voltage across the capacitor (v csen ) in terms of the inductor current (i l ). figure 117. a simplified schema tic illustrating the use of two shunt resistors to create a desired shunt value figure 118. increasing the number of shunt resistors in parallel to create a shunt resistor value reduces the power dissipated by each shunt resistor. 0.001 0.004 (eq. 22) p shuntres v shunt_range 2 r sense 0.002 0.004 0.002 vinp vinm lo rdcr csen rsen dcr circuit adc 16-bit buck regulator fb phase load rsen + rdcr (eq. 23) x c f () 1 j ? f () ? c ? x l f () j ? f () ? l ? (eq. 24) v dcr f () r dcr j ? f () ? l ? ? ? ? i l ? (eq. 25) v c f () j ? f () ? l ? r dcr ? ?? 1j ? f () ? c sen ? r sen ? ? ? ? ? ? ? ? i l ? r dcr 1 jwf () ? l ? () r dcr ? ? ? ? ? ? ? 1j ? f () ? c sen ? r sen ? ? ? ? ? ? ? ? ? ? ? i l ? isl28023 51 fn8389.4 june 17, 2015 submit document feedback the relationship between the inductor load current (i l ) and the voltage across the capacitor simplifies if the following component selection holds true; if equation 26 holds true, the numerator and denominator of the fraction in equation 25 cancels reducing the voltage across the capacitor to the equation represented in equation 27 . most inductor datasheets will sp ecify the average value of the r dcr for the inductor. r dcr values are usually sub 1m with a tolerance averaging 8%. common chip capacitor tolerances average to 10%. inductors are constructed out of metal. metal has a high temperature coefficient. the temperature drift of the inductor value could cause the dcr circuit to be untuned. an untuned circuit results in inaccurate cu rrent measurements along with a chop signal bleeding into the measurement. to counter the temperature variance, a temperature sensor may be incorporated into the design to track the change in component values. a dcr circuit is good for gross current measurements. as discussed, inductors and capacitors have high tolerances and are temperature dependent which will result in less than accurate current measurements. in figure 119 , there is a resistor in series with the isl28023 negative shunt terminal, vinm, with the value of r sen + r dcr. the resistor?s purpose is to counter the effects of the bias current from creating a voltage offset at the input of the adc. layout the layout of a current measuring system is equally important as choosing the correct sense resi stor and the correct analog converter. poor layout techniques can result in severed traces, signal path oscillations, magnetic contamination which all contribute to poor system performance. trace width matching the current carrying density of a copper trace with the maximum current that will pass through is critical in the performance of the system. neglecting the current carrying capability of a trace will result in a large temperature rise in the trace, and the loss in system efficiency due to the increase in resistance of the co pper trace. in extreme cases, the copper trace could be severed because the trace could not pass the current. the current carrying capability of a trace is calculated using equation 28 . i max is the largest current expect ed to pass through the trace. ? t is the allowable temperature rise in celsius when the maximum current passes through the trace. trace thickness is the thickness of the trace specified to the pcb fabricator in mils. a typical thickness for general current carrying applications (<100ma) is 0.5oz copper or 0.7mils. for larg er currents, the trace thickness should be greater than 1.0oz or 1.4mils. a balance between thickness, width and cost needs to be achieved for each design. the coefficient k in equation 28 changes depending on the trace location. for external traces, the value of k equals 0.048 while for internal traces the value of k reduces to 0.024. the k values and equation 28 are stated per the ansi ipc-2221(a) standards. trace routing it is always advised to make the distance between voltage source, sense resistor and load as close as possible. the longer the trace length between components will result in voltage drops between components. the addition al resistance will reduce the efficiency of a system. the bulk resistance, ? , of copper is 0.67 /in or 1.7 /cm at +25c. the resistance of trac e can be calculated from equation 29 . figure 120 illustrates each dimension of a trace. for example, assume a trace has 2oz of copper or 2.8mil thickness, a width of 100mil and a length of 0.5in. using equation 29 , the resistance of the trace is approximately 2m . assume 1a of current is passi ng through the trace. a 2mv voltage drop would result from trace routing. current flowing through a conducto r will take the path of least resistance. when routing a trace, avoid orthogonal connections for current bearing traces. (eq. 26) l r dcr c sen r sen ? v c r dcr i l ? trace width imax k ? t 0.44 ? ? ? ? ? ? ? 1 0.725 trace thickness figure 120. illustration of th e trace dimensions for a strip line trace figure 121. avoid routing orthogonal connections for traces that have high current flows (eq. 29) r trace ? trace length trace width trace thickness ? ? t r a c e l e n g t h trace width trace thickness current flow isl28023 52 fn8389.4 june 17, 2015 submit document feedback orthogonal routing for high current flow traces will result in current crowding, localized heatin g of the trace and a change in trace resistance. the utilization of arcs and 45 trac es in routing large current flow traces will maintain uniform curre nt flow throughout the trace. figure 122 illustrates the routing technique. connecting sense traces to the current sense resistor ideally, a 4 terminal current sense resistor would be used as the sensing element. four terminal sensor resistors can be hard to find in specific values and in sizes. often a two terminal sense resistor is designed into the application. sense lines are high impedance by definition. the connection point of a high impedance line reflects the voltage at the intersection of a current bear ing trace and a high impedance trace. the high impedance trace should connect at the intersection where the sense resistor meets the landing pad on the pcb. the best place to make current sense line connection is on the inner side of the sense resistor foot print. the illustration of the connection is shown in figure 123 . most of the current flow is at the outer edge of the footprint. the current ceases at the point the sense resistor connects to the landing pad. assume the sense resistor connects at the middle of each landing pad, this leaves the inner half of each landing pad with little current flow. with little current flow, the inner half of each landing pad is classified as high impedance and perfect for a sense connection. current sense resistors are often smaller than the width of the traces that connect to the footpr int. the trace connecting to the footprint is tapered at a 45 angle to control the uniformity of the current flow. magnetic interference the magnetic field generated from a trace is directly proportional to the current passing through th e trace and the distance from the trace the field is being measured at. figure 124 illustrates the direction the magnetic field flows versus current flow. the equation in figure 124 determines the magnetic field, b, the trace generates in relation to the current passing through the trace, i, and the distance the ma gnetic field is being measured from the conductor, r. the permeability of air, o , is 4 ? *10 -7 h/m. when routing high current traces, avoid routing high impedance traces in parallel with high cu rrent bearing traces. a means of limiting the magnetic interference from high current traces is to closely route the paths connected to and from the sense resistor. the magnetic fields will cancel outside the two traces and add between the two traces. figure 125 illustrates a magnetic field insensitive layout. if possible, do not cross traces with high current. if a trace crossing cannot be avoided, cro ss the trace in an orthogonal manner and the furthest layer from the current bearing trace. the interference from the current bearing trace will be limited. figure 122. use arcs and 45 de gree traces to safely route traces with large current flows c u r r e n t f l o w current flow sense resistor sense trace sense trace landing pad landing pad current bearing trace current bearing trace b ? o i ? 2 ? ? r ? isl28023 53 fn8389.4 june 17, 2015 submit document feedback a trace as a sense resistor in previous sections, the resist ance and the current carrying capabilities of a trace were di scussed. in high current sense applications, a design may utilize the resistivity of a current sense trace as the sense resistor. this section will discuss how to design a sense resistor from a copper trace. suppose an application needs to measure current up to 200a. the design requires the least amount of voltage drop for maximum efficiency. the full-scale voltage range of 40mv is chosen. from ohms law, the sense resistor is calculated to be 200 . the power rating of the resistor is calculated to be 8w. assume the pcb trace thickness of the board equals 2oz/2.8mils and the maximum temperature rise of the trace is 20c. using equation 28 , the calculated trace width is 2.192in. the trace width, thickness and the desired sense resistor value is known. utilizing equation 29 , the trace length is calculated to be 1.832in. figure 126 illustrates a layout ex ample of a current sense resistor defined by a pcb trace. the serpentine pattern of the resistor reduces current crowding as well as limiting the magnetic interference caused by the current flowing through the trace. . for the example discussed, the width of the trace in figure 126 illustration would equal 2.192in and the length between the sense lines equals 1.832in. the width of the resistor is long for some applications. a means of shortening the trace width is to connect two traces in parallel. for calculation ease, assume the resistive traces are routed on the outside layers of a pcb. using equations 28 and 29 , the width of the trace is reduced from 2.192in to 1.096in. when using multiple layers to create a trace resistor, use multiple vias to keep the trace potentials between the two conductors the same. vias are hi ghly resistive compared to a copper trace. multiple vias should be employed to lower the voltage drop due to current flowing through resistive vias. figure 127 illustrates a layout technique for a multiple layered trace sense resistor. figure 125. closely routed traces that connect to the sense resistor reduces the magnetic interference sourced from the current flowing through the traces sense resistor s e n s e t r a c e s e n s e t r a c e l a n d i n g p a d l a n d i n g p a d current flow current flow t o t h e s e n s e r e s i s t o r f r o m t h e s e n s e r e s i s t o r b to b from ? b to b from ? b to b from ? to sense circuitry current ? flow ? in current ? flow ? out sense ? neg( \ ) sense ? pos(+) the ? length ? of ? the ? trace ? between ? the ? two ? sense ? lines ? defines ? the ? sense ? resistor ? value. top bottom trace trace via via trace via (a) cross section view (b) top view pcb pcb isl28023 54 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8389.4 june 17, 2015 for additional products, see www.intersil.com/en/products.html submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o the web to make sure that you have the latest revision. date revision change june 17, 2015 fn8389.4 add related literature section to page 1. added dpm portfolio comparison table on page 5. removed typical applications section (which included figures 127 through 135) and made into an appnote (an1955). october 27, 2014 fn8389.3 on page 37 vbus_ov_ot_set [1st paragraph) changed the step size to 5.71 and added a sentence. added a column to the table 24 . changed the table title on table 30 to vshunt_oc_set ( page 38 ) june 27, 2014 fn8389.2 removed isl28023eval2z information and added ISL28023EVKIT1Z (evaluation kit) to the ordering information on page 3 . june 12, 2014 fn8389.1 changed auxn to auxm in figures 1 , 112 , 127, 128, 129, 131, 132, 133, and 135. updated notes 4 and 5 to correct package notes required. page 51 the equation reference of 15 becomes 28 figure 120 changed "of a strip" to "for a strip" in the title. figure 124 changed "current flow out" to "a current flow out" in the title. equation 25 was updated by adding ? i l ? to the first portion of equation. added evaluation board information to ordering information on page 3 . may 2, 2014 fn8389.0 initial release. isl28023 55 fn8389.4 june 17, 2015 submit document feedback package outline drawing l24.4x4d 24 lead quad flat no-lead plastic package rev 3, 11/13 0 . 90 0 . 1 5 c 0 . 2 ref typical recommended land pattern 0 . 05 max. ( 24x 0 . 6 ) detail "x" ( 24x 0 . 25 ) 0 . 00 min. ( 20x 0 . 5 ) ( 2 . 50 ) side view ( 3 . 8 typ ) base plane 4 top view bottom view 7 12 24x 0 . 4 0 . 1 13 4.00 pin 1 18 index area 24 19 4.00 2.5 0.50 20x 4x see detail "x" - 0 . 05 + 0 . 07 24x 0 . 23 2.45 (+ 0.10mm) pin #1 corner (c 0 . 25) 1 seating plane 0.08 c 0.10 c c 0.10 m c a b a b (4x) 0.15 located within the zone indicated. the pin #1 indentifier may b e unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metalliz ed terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (- 0.15mm) |
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